FUNCTIONAL DESCRIPTION
The MACH220 consists of eight PAL blocks connected
by a switch matrix. There are 48 I/O pins and 4
dedicated input pins feeding the switch matrix. These
signals are distributed to the four PAL blocks for efficient
design implementation. There are 4 clock pins that can
also be used as dedicated inputs.
All inputs and I/O pins have built-in pull-up resistors.
While it is always good design practice to tie unused
pins high or low, the pull-up resistors provide design
security and stability in the event that unused pins are
left disconnected.
M
0
Table 1. Logic Allocation
Macrocell
Output
Buried
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
Available
Clusters
C
0
, C
1
, C
2
C
0
, C
1
, C
2
, C
3
C
1
, C
2
, C
3
, C
4
C
2
, C
3
, C
4
, C
5
C
3
, C
4
, C
5
, C
6
C
4
, C
5
, C
6
, C
7
C
5
, C
6
, C
7
, C
8
C
6
, C
7
, C
8
, C
9
C
7
, C
8
, C
9
, C
10
C
8
, C
9
, C
10
, C
11
C
9
, C
10
, C
11
C
10
, C
11
The PAL Blocks
Each PAL block in the MACH220 (Figure 1) contains a
48-product-term logic array, a logic allocator, 6 output
macrocells, 6 buried macrocells, and 6 I/O cells. The
switch matrix feeds each PAL block with 26 inputs. This
makes the PAL block look effectively like an independ-
ent “PAL26V12” with 6 buried macrocells.
In addition to the logic product terms, two output enable
product terms, an asynchronous reset product term,
and an asynchronous preset product term are provided.
One of the two output enable product terms can be
chosen within each I/O cell in the PAL block. All flip-flops
within the PAL block are initialized together.
The Macrocell
The MACH220 has two types of macrocell: output and
buried. The output macrocells can be configured as
either registered, latched, or combinatorial, with pro-
grammable polarity. The macrocell provides internal
feedback whether configured with or without the flip-
flop. The registers can be configured as D-type or
T-type, allowing for product-term optimization.
The flip-flops can individually select one of four
clock/gate pins, which are also available as data inputs.
The registers are clocked on the LOW-to-HIGH
transition of the clock signal. The latch holds its data
when the gate input is HIGH, and is transparent when
the gate input is LOW. The flip-flops can also be
asynchronously initialized with the common asynchro-
nous reset and preset product terms.
The buried macrocells are the same as the output
macrocells if they are used for generating logic. In that
case, the only thing that distinguishes them from the
output macrocells is the fact that there is no I/O cell
connection, and the signal is only used internally. The
buried macrocell can also be configured as an input
register or latch.
The Switch Matrix
The MACH220 switch matrix is fed by the inputs and
feedback signals from the PAL blocks. Each PAL block
provides 12 internal feedback signals and 6 I/O
feedback signals. The switch matrix distributes these
signals back to the PAL blocks in an efficient manner
that also provides for high performance. The design
software automatically configures the switch matrix
when fitting a design into the device.
The Product-Term Array
The MACH220 product-term array consists of 48
product terms for logic use, and 4 special-purpose
product terms. Two of the special-purpose product
terms provide programmable output enable, one
provides asynchronous reset, and one provides
asynchronous preset.
The I/O Cell
The I/O cell in the MACH220 consists of a three-state
output buffer. The three-state buffer can be configured
in one of three ways: always enabled, always disabled,
or controlled by a product term. If product term control is
chosen, one of two product terms may be used to
provide the control. The two product terms that are
available are common to all I/O cells in a PAL block.
These choices make it possible to use the macrocell as
an output, an input, a bidirectional pin, or a three-state
output for use in driving a bus.
The Logic Allocator
The logic allocator in the MACH220 takes the 48 logic
product terms and allocates them to the 12 macrocells
as needed. Each macrocell can be driven by up to 16
product terms. The design software automatically
configures the logic allocator when fitting the design into
the device.
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
6
MACH220-10/12/15/20
LATTICE [ LATTICE SEMICONDUCTOR ]
