From I/O Pin
PAL-Block
Asynchronous
Preset
1
0
AP
D/T/L
1
0
Sum of Products
From Logic
IC Allocator
CLK
Q
0
CLK
AR
n
PAL-Block
Asynchronous
Reset
To
Switch
Matrix
14051K-030
Figure 5. Buried Macrocell (MACH 2 only)
From Logic
Allocator
From
Logic
Allocator
n
AP
AR
n
D
Q
CLKÂ
0
CLÂK
n
To Switch
Matrix
To Switch
Matrix
a. Combinatorial
b. D-type register
From I/O
Cell
n
From Logic
Allocator
AP
AR
T
Q
AP
AR
CLK
0
D
Q
CLK
n
CLK
0
CLK
n
To Switch
Matrix
To Switch
Matrix
c. T-type register
d. Input register
From I/O
Cell
From
Logic
Allocator
n
AP
AR
L
Q
AP
L
CLK
Q
0
G
CLK
n
CLK
0
G
CLK
n
AR
To Switch
Matrix
To Switch
Matrix
e. Latch
f. Input latch
14051K-006
Figure 6. Buried Macrocell Configurations (MACH 2 only)
MACH 1 & 2 Families
10
LATTICE [ LATTICE SEMICONDUCTOR ]
