PAL-Block
Asynchronous
Preset
Sum of Products
From Logic
IC Allocator
CLK0
CLKn
PAL-Block
Asynchronous
Reset
1
0
AP
D/T/L Q
From I/O Pin
1
0
AR
To
Switch
Matrix
14051K-030
Figure 5. Buried Macrocell (MACH 2 only)
From Logic
Allocator
CLKÂ0
To Switch
Matrix
CLÂKn
To Switch
Matrix
a. Combinatorial
From Logic
Allocator
CLK0
CLKn
To Switch
Matrix
c. T-type register
From
Logic
Allocator
CLK0
CLKn
To Switch
Matrix
To Switch
Matrix
e. Latch
f. Input latch
14051K-006
From
Logic
Allocator
n
n
D
AP
Q
AR
b. D-type register
AP
From I/O
Cell
Q
D
AR
CLK0
CLKn
To Switch
Matrix
d. Input register
AP
From I/O
Cell
Q
L
G
AR
CLK0
CLKn
G
AP
Q
AR
AP
Q
n
T
n
L
AR
Figure 6. Buried Macrocell Configurations (MACH 2 only)
10
MACH 1 & 2 Families