FINAL
COM’L: -12/15/20, Q-20/25
MACH435-12/15/20, Q-20/25
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
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84 Pins in PLCC
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128 Macrocells
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12 ns tPD
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83.3 MHz fCNT
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70 Inputs with pull-up resistors
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64 Outputs
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192 Flip-flops
— 128 Macrocell flip-flops
— 64 Input flip-flops
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Up to 20 product terms per function, with XOR
Lattice Semiconductor
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Flexible clocking
— Four global clock pins with selectable edges
— Asynchronous mode available for each
macrocell
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8 “PAL33V16” blocks
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Input and output switch matrices for high
routability
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Fixed, predictable, deterministic delays
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Pin compatible with MACH130, MACH131,
MACH230, and MACH231
GENERAL DESCRIPTION
The MACH435 is a member of our high-performance
EE CMOS MACH 4 family. This device has approxi-
mately twelve times the macrocell capability of the
popular PAL22V10, with significant density and func-
tional features that the PAL22V10 does not provide.
The MACH435 consists of eight PAL blocks intercon-
nected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.
The MACH435 has macrocells that can be configured
as synchronous or asynchronous. This allows designers
to implement both synchronous and asynchronous logic
together on the same device. The two types of design
can be mixed in any proportion, since the selection on
each macrocell affects only that macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.
The MACH435 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.
Publication#
17469
Rev.
E
Issue Date:
May 1995
Amendment
/0
LATTICE [ LATTICE SEMICONDUCTOR ]
