Lattice Semiconductor
ORCA ORT8850 Data Sheet
LVDS Reference Clock
The reference clock for the ORT8850 SERDES is an LVDS input (SYS_CLK_[P:N]). This reference clock can run in
the range from 63.00 MHz to 106.25 MHz and is used to clock the entire Embedded Core. This clock is also avail-
able in the FPGA interface as the output signal FPGA_SYSCLK at the Embedded Core/FPGA Logic interface.
The supported range of reference clock frequencies will drive the internal and link serial rates from 504 MHz to 850
MHz. For standard SONET applications a reference clock rate of 77.76 MHz will allow the ORT8850 to communi-
cate with standard SONET devices. If the ORT8850 is communicating with another ORT8850, the reference clock
can run anywhere in the defined range. When using a non 77.76 MHz reference clock, the frame pulse will now
need to be derived from the non standard rate thus making the frame pulse rate not 8 kHz, but rather a single clock
pulse every 9720 clock cycles.
System Considerations for Reference Clock Distribution
There are two main system clocking architectures that can be used with the ORT8850 at the system level to pro-
vide the LVDS reference clocks. The recommended approach is to distribute a single reference clock to all boards.
However, independent clocks can be used on each board provided that they are matched with sufficient accuracy
and the alignment is not used. These two approaches are summarized in the following paragraphs
Distributed Clocking
A distributed clock architecture, shown in Figure 5, uses a single source for the system reference clock. This single
source drives all devices on both the line and switch sides of the backplane. Typically this is a lower speed clock
such as a 19.44 MHz signal. An external PLL on each board or and internal ORT8850 FPGA PLL is then used to
multiply the clock to the desired reference clock rate (i.e. by 4x to 77.76 MHz if the distributed clock is at 19.44
MHz). Using this type of clock architecture the ORT8850 data channels are fully synchronous and no domain trans-
fer is required from the transmitter to the receiver.
Figure 5. Distributed Clock Architecture
Port
Cards
19.44 Mhz.
ORT8850
(SERDES at
622 Mbps)
Oscillator
Fabric
Cards
FPGA
PPLL (x4)
FPGA
LVDS
PIO
PIO_OUT_P
PIO_OUT_N
SYS_CLK_N SYS_CLK_P
Buffer
77.76 Mhz
Clock (Differential)
19.44 Mhz
Clock Source
System Diagram
Independent Clocking
An independent clock architecture uses independent clock sources on each ORT8850 board. With this architec-
ture, for the SERDES to sample correctly the independent oscillators must be within reference clock tolerance
requirements for the Clock and Data Recovery (CDR) to correctly sample the incoming data and recover data and
clock. The local reference clock and the recovered clock will not be synchronous since they are created from a dif-
ferent source. The alignment FIFO uses the recovered clock for write and the local reference clock for read. Due to
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LATTICE [ LATTICE SEMICONDUCTOR ]
