Lattice Semiconductor
ORCA ORT8850 Data Sheet
AA.This same scheme is used for channels groupings of AC/AD, BA/BB, and BC/BD. For quad protection when the
alignment FIFOs are to be used, the protection switching must be done in FPGA logic.
Figure 9. Parallel Protection Switching
SONET and
Transmit
Receive
HSI Blocks
SONET and
HSI Blocks
Work
Parallel RX Data
(To FPGA)
Parallel TX Data
(From FPGA)
Channel AA
Work
Channel AA
Protect
Channel AB
Etc.
Protect
Channel AB
Etc.
Work/Protect Select
LVDS protection switching (Figure 10) takes place at the LVDS buffer before the serial data is sent into the CDR.
The selection is between the main LVDS buffer and the protect LVDS buffer. The main LVDS buffer provide the
main receive data on RXDxx_W_[P:N] while the protect LVDS buffers provide protection receive data on
RXDxx_P_[P:N]. When operating using the main LVDS buffers (default) no status information is available on the
protect LVDS buffers since the serial stream must reach the SONET framer before status information is available
on the data stream. The same is also true for the main LVDS buffers when operating with the protect buffers.
Figure 10. LVDS Protection Switching
Transmit
Receive
To CDR
Work (from Work LVDS Buffer)
Work (to Work LVDS Buffer)
From TX SERDES
Protect (from Protect LVDS Buffer)
Protect (to Protect LVDS Buffer)
Work/Protect Select
See Table 17 and Table 18 and the accompanying text for details and register settings for the protection switching
options.
FPSC Configuration - Overview
Configuration of the ORT8850 occurs in two stages: FPGA bit stream configuration and embedded core setup.
FPGA Configuration - Overview
Prior to becoming operational, the FPGA goes through a sequence of states, including power-up, initialization, con-
figuration, start-up, and operation. The FPGA logic is configured by the standard FPGA bit stream configuration
means as discussed in the Series 4 FPGA data sheet. The options for the embedded core are set via registers that
are accessed through the FPGA system bus. The system bus can be driven by an external PPC compliant micro-
processor via the MPI block or via a user master interface in FPGA logic. A simple IP block, that drives the system
by using the user interface and uses very little FPGA logic, is available in the MPI/System Bus technical note
(TN1017). This IP block sets up the embedded core via a state machine and allows the ORT8850 to work in an
independent system without an external MicroProcessor Interface.
Embedded Core Setup
All options for the operation of the core are configured according to the memory map shown in Table 19.
During the power-up sequence, the ORT8850 device (FPGA programmable circuit and the core) is held in reset. All
the LVDS output buffers and other output buffers are held in 3-state. All Flip-Flops in the core area are in reset
state, with the exception of the boundry-scan shift registers, which can only be reset by boundary-scan reset. After
power-up reset, the FPGA can start configuration. During FPGA configuration, the ORT8850 core will be held in
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LATTICE [ LATTICE SEMICONDUCTOR ]
