Lattice Semiconductor
ORCA ORT8850 Data Sheet
Pin Information
This section describes the pins and signals that perform FPGA-related functions. During configuration, the user-
programmable I/Os are 3-stated and pulled up with an internal resistor. If any FPGA function pin is not used (or not
bonded to package pin), it is also 3-stated and pulled up after configuration.
Table 32. FPGA Common-Function Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD33
3.3 V positive power supply. This power supply is used for 3.3 V configuration RAMs and internal
PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on
the board for proper operation.
—
VDD15
VDDIO
VSS
—
—
—
I
1.5 V positive power supply for internal logic.
Positive power supply used by I/O banks.
Ground.
PTEMP
RESET
Temperature sensing diode pin. Dedicated input.
During configuration, RESET forces the restart of configuration and a pull-up is enabled. After con-
figuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC
latches/FFs to be asynchronously SET/RESET.
I
O
I
CCLK
DONE
In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration
data in.
In the slave or readback after configuration, CCLK is input synchronous with the data on DIN or
D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or
system bus modes.
I
As an input, a low level on DONE delays FPGA start-up after configuration.*
As an active-high, open-drain output, a high level on this signal indicates that configuration is com-
plete. DONE has an optional pull-up resistor.
O
PRGM
PRGM is an active-low input that forces the restart of configuration and resets the boundary-scan
circuitry. This pin always has an active pull-up.
I
I
RD_CFG
This pin must be held high during device initialization until the INIT pin goes high. This pin always
has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-
states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL func-
tion as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on
RD_CFG will initiate readback of the configuration data, including PFU output states, starting with
frame address 0.
RD_DATA/TDO
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data
out. If used in boundary-scan, TDO is test data out.
O
O
CFG_IRQ/MPI_IRQ
During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ
(active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low inter-
rupt request output, when the MPI is used.
1. The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activa-
tion of all user I/Os) is controlled by a second set of options.
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