Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
To
Adjacent
Macrocell
11
0X
10
OE
V
CC
11
10
00
01
SL0
X
SG1
R
11
0X
10
SE
G
N AL
EW D
EV
D
ES IC
IG ES
N F
S O
I/O
X
D
Q
Q
SL1
X
CLK
10
11
0X
SL0
X
*SG1
*In macrocells MC
0
and MC
7
, SG1 is replaced by SG0 on the feedback multiplexer.
From
Adjacent
Pin
16493E-2
Figure 1. PALCE16V8 Macrocell
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, it is always disabled.
With the exception of MC
0
and MC
7
, a macrocell configured as a dedicated input derives the
input signal from an adjacent I/O. MC
0
derives its input from pin 11 (OE) and MC
7
from pin 1
(CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
0
through SL0
7
and SL1
0
through SL1
7
). SG0
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0
x
, in
conjunction with SG1, selects the configuration of the macrocell, and SL1
x
sets the output as
either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
x
are the control signals for all four multiplexers. In
MC
0
and MC
7
, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
the adjacent pin for MC
7
and OE the adjacent pin for MC
0
.
U
PALCE16V8 and PALCE16V8Z Families
3
LATTICE [ LATTICE SEMICONDUCTOR ]
