Austin LynxTM SIP Non-Isolated dc-dc Power Modules:
3.0 Vdc - 5.5 Vdc Input, 0.9 Vdc - 3.3 Vdc Output, 10 A
Data Sheet
March 28, 2008
Test Configurations
Design Considerations
Input Source Impedance
TO OSCILLOSCOPE
To maintain low-noise and ripple at the input voltage, it is
critical to use low ESR capacitors at the input to the module.
18 shows the input ripple voltage (mVp-p) for various output
L
VI (+)
1 µH
models using a 150 µF low ESR polymer capacitor (Pana-
sonic p/n: EEFUE0J151R, Sanyo p/n: 6TPE150M) in parallel
with 47 µF ceramic capacitor (Panasonic p/n: ECJ-
5YB0J476M,
CS 220 μF
ESR < 0.1 Ω
@ 20 °C, 100 kHz
2 x 100µF
Tantalum
BATTERY
Taiyo Yuden p/n: CEJMK432BJ476MMT). Figure 19 depicts
much lower input voltage ripple when input capacitance is
VI (–)
increased to 450 µF (3 x 150 µF) polymer capacitors in par-
allel with 94 µF (2 x 47 µF) ceramic capacitor.
Note: Measure input reflected ripple current with a simulated source
inductance (LTEST) of 1µH. Capacitor CS offsets possible bat-
tery impedance. Measure current as shown above.
The input capacitance should be able to handle an AC ripple
current of at least:
Vout
Vout
Figure 15. Input Reflected Ripple Current Test Setup.
Irms = Iout ---------- 1 – ----------
Arms
Vin
Vin
200
150
100
50
COPPER STRIP
VO
10 µF
1µF
RESISTIVE
LOAD
SCOPE
CERAMIC
TANTALUM
GND
V
I
= 5 V
V
I = 3.3 V
Note: Scope measurements should be made using a BNC socket,
with a 10 µF tantalum capacitor and a 1 µF ceramic capcitor.
Position the load between 51 mm and 76 mm (2 in and 3 in)
from the module
0
0.5
1
1.5
2
2.5
O (Vdc)
3
OUTPUT VOLTAGE, V
Figure 16. Peak-to-Peak Output Ripple Measurement
Test Setup.
Figure 18. Input Voltage Ripple for Various
Output Models, IO = 10 A
(CIN = 150 µF polymer // 47 µF ceramic).
CONTACT AND
DISTRIBUTION LOSSES
100
75
50
25
0
VI
VO
II
IO
LOAD
SUPPLY
GND
CONTACT RESISTANCE
V
I
= 5 V
Note: All voltage measurements to be taken at the module termi-
nals, as shown above. If sockets are used then Kelvin con-
nections are required at the module terminals to avoid
measurement errors due to socket contact resistance.
V
I = 3.3 V
0.5
1
1.5
2
2.5
3
OUTPUT VOLTAGE, V
O
(Vdc)
Figure 17. Output Voltage and Efficiency Test Setup.
Figure 19. Input Voltage Ripple for Various
Output Models, IO = 10 A
[V
– V ] × I
O(-) O
⎠
– V ] × I
I(-) I
O(+)
⎛
⎞
η = ------------------------------------------------ × 100
(CIN = 3x150 µF polymer // 2x47 µF ceramic).
⎝
[V
I(+)
Lineage Power
8
LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
