Figure 1. Operational Amplifier Protection
Input Differential Voltage limited to 0.8V (typ) by DPADs D
1
and D
2
. Common
Mode Input voltage limited by DPADs D
3
and D
4
to ±15V.
Figure 2. Sample and Hold Circuit
Typical Sample and Hold circuit with clipping. DPAD diodes reduce offset
voltages fed capacitively from the JFET switch gate.
FIGURE 1
DPAD10
D1
D3
D2
D4
-
OP-27
+
FIGURE 2
+V
DPAD1
D1
-V
D2
2N4117A
2N4393
C
R
V
OUT
+V
e
in
+15V -15V
CONTROL
SIGNAL
TO-72
Four Lead
0.195 DIA.
0.175
0.030
MAX.
0.230
DIA.
0.209
0.150
0.115
TO-78
0.305
0.335
0.335
0.370
MAX.
0.040 0.165
0.185
MIN. 0.500
SEATING
PLANE
0.200
0.100
3 4
5
7
SOIC
0.014
0.018
1
2
0.021
3
4
0.150
0.157
8
7
6
5
0.050
0.189
0.196
0.016
0.019
DIM. A
0.016
0.021
DIM. B
0.029
0.045
1
4 LEADS
0.019 DIA.
0.016
0.100
0.500 MIN.
0.0040
0.0098
0.2284
0.2440
DIMENSIONS IN
INCHES
0.050
2
1
3
4
0.0075
0.0098
45°
0.046
0.036
45°
0.100
0.048
0.028
0.028
0.034
1.
2.
Absolute maximum ratings are limiting values above which serviceability may be impaired.
The DPAD type number denotes its maximum reverse current value in pico amperes. Devices with I
R
values intermediate to those
shown are available upon request.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems
• 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
