LTC3547
U
W U U
APPLICATIO S I FOR ATIO
Thermal Considerations
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3547. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
In a majority of applications, the LTC3547 does not dis-
sipate much heat due to its high efficiency. In the unlikely
event that the junction temperature somehow reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
1. Does the capacitor C connect to the power V (Pin 3)
The goal of the following thermal analysis is to determine
whetherthepowerdissipatedcausesenoughtemperature
risetoexceedthemaximumjunctiontemperature(125°C)
of the part. The temperature rise is given by:
IN
IN
and GND (Pin 5) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective C
and L closely connected?
OUT
T
= P • θ
(6)
RISE
D
JA
The (–) plate of C
returns current to GND and the
OUT
Where P is the power dissipated by the regulator and
JA
to the ambient temperature.
D
(–) plate of C .
IN
θ
is the thermal resistance from the junction of the die
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C and a ground sense
OUT1
The junction temperature, T , is given by:
J
line terminated near GND (Pin 5). The feedback sig-
nals V and V should be routed away from noisy
T = T
+ T
AMBIENT
(7)
FB1
FB2
J
RISE
components and traces, such as the SW lines (Pins 4
and 6), and their trace length should be minimized.
As a worst-case example, consider the case when the
LTC3547 is in dropout on both channels at an input volt-
age of 2.7V with a load current of 300mA and an ambi-
ent temperature of 70°C. From the Typical Performance
4. Keep sensitive components away from the SW pins if
possible. The input capacitor C and the resistors R1,
IN
R2, R3 and R4 should be routed away from the SW
Characteristics graph of Switch Resistance, the R
DS(ON)
traces and the inductors.
of the main switch is 0.9Ω. Therefore, power dissipated
by each channel is:
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
2
P = I
• R
= 81mV
DS(ON)
D
OUT
Given that the thermal resistance of a properly soldered
DFN package is approximately 76°C/W, the junction
temperature of an LTC3547 device operating in a 70°C
ambient temperature is approximately:
current path of C or C
.
IN
OUT
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
T = (2 • 0.081W • 76°C/W) + 70°C = 82.3°C
J
which is well below the absolute maximum junction tem-
perature of 125°C.
connected to V or GND.
IN
3547fa
12
Linear Systems [ Linear Systems ]
