LTC2960
APPLICATIONS INFORMATION
provide effective pull-down without excessively loading the
pull-up circuitry. A 100k resistor from output to ground is
satisfactory for most applications. When the status outputs
are high, power is dissipated in the pull-down resistors.
If V
CC
falls below the falling UVLO threshold, the outputs
are pulled to ground. The outputs are guaranteed to stay
low for V
CC
≥ 1.2V regardless of the output logic configura-
tion. When V
CC
< 1.2V, the active pull-up output behaves
similarly to an open-drain output with a pull-up resistor.
LTC2960-3
DV
CC
1.6V TO 5.5V
and
MR
is a solution to this issue. The
MR
input can be
pulled to 36V maximum and will not affect the internal
circuitry. Input
MR
is often pulled down through the use
of a pushbutton switch.
SELECTING THE RESET TIMEOUT PERIOD
Use the RT input (LTC2960-1/ LTC2960-2) to select between
two fixed reset timeout periods. Connect RT to ground for
a 15ms timeout. Connect RT to V
CC
for a 200ms timeout.
The reset timeout period occurs after the ADJ input is
driven above threshold and the
MR
input transitions above
its logic threshold. After the reset timeout period, the
RST
output is allowed to pull up to a high state as shown in
Figure 5. The RT input is replaced by the DV
CC
input in
the LTC2960-3/LTC2960-4 options and the reset timeout
period defaults to 200ms.
ADJ
15ms
0.4V
+
–
(a). PUSH-PULL CONFIGURATION
OUT
IN
+
LTC2960-3
DV
CC
6.3V MAX
RST,
RT = GND
200ms
RST,
RT = V
CC
2960 F05
0.4V
+
–
(b). OPEN-DRAIN CONFIGURATION
OUT
Figure 5. Selectable Reset Timeout Period
IN
+
EXTERNAL HYSTERESIS
2960 F04
Figure 4. LTC2960-3 (LTC2960-4)
RST
and OUT Outputs are
Configurable as Push-Pull or Open-Drain
MANUAL RESET INPUT
When ADJ is above its reset threshold and the manual
reset input (MR) is pulled low, the
RST
output is forced
low.
RST
remains low for the selected reset timeout period
after the manual reset input is released and pulled high.
The manual reset input is pulled up internally through a
1μA current source to an internal bias voltage (see Elec-
trical Characteristics). If external leakage currents have
the ability to pull down the manual reset input below its
logic threshold, a pull-up resistor placed between V
CC
The LTC2960 IN
+
comparator hysteresis is 20mV (V
+HYS
),
or 5% referred to V
TH
. Certain applications require more
than the built-in native hysteresis. The application sche-
matic in Figure 6 adds one additional resistor (R6) to a
typical attenuator network. The procedure below is used
to determine a value for R6 to provide an increase over
the native hystereis. In this example, it is desired to double
the native hysteresis from 300mV to 600mV and achieve
a falling threshold of 6V.
Before including R6, the rising threshold (V
R
) is 6.293V
while the falling threshold (V
F
) is 5.993V. The hysteresis
referred to V
A
is calculated from:
⎛
R4
⎞
V
HYST
(
VA
)
=
V
PHYS
⎜
1+
⎟ =20mV •15 =
300mV
⎝
R5
⎠
2960f
10
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
