LTC2379-18
PIN FUNCTIONS
CHAIN (Pin 1):
Chain Mode Selector Pin. When low, the
LTC2379-18 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2379-18 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by 0V
DD
.
V
DD
(Pin 2):
2.5V Power Supply. The range of V
DD
is
2.375V to 2.625V. Bypass V
DD
to GND with a 10μF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16):
Ground.
IN
+
, IN
–
(Pins 4, 5):
Positive and Negative Differential
Analog Inputs.
REF (Pin 7):
Reference Input. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47μF ceramic capacitor
(X5R, 0805 size).
REF/DGC (Pin 8):
When tied to REF digital gain compression
,
is disabled and the LTC2379-18 defines full-scale according
to the ±V
REF
analog input range. When tied to GND, digital
gain compression is enabled and the LTC2379-18 defines
full-scale with inputs that swing between 10% and 90%
of the ±V
REF
analog input range.
CNV (Pin 9):
Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by 0V
DD
.
BUSY (Pin 11):
BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by 0V
DD
.
RDL/SDI (Pin 12):
When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by 0V
DD
.
SCK (Pin 13):
Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by 0V
DD
.
SDO (Pin 14):
Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by 0V
DD
.
OV
DD
(Pin 15):
I/O Interface Digital Power. The range of
OV
DD
is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OV
DD
to GND with a 0.1μF capacitor.
GND (Exposed Pad Pin 17 – DFN Package Only):
Ground.
Exposed pad must be soldered directly to the ground plane.
FUNCTIONAL BLOCK DIAGRAM
V
DD
= 2.5V
REF = 5V
LTC2379-18
CHAIN
SDO
RDL/SDI
SCK
OV
DD
= 1.8V to 5V
IN
+
+
18-BIT SAMPLING ADC
IN
–
–
SPI
PORT
CONTROL LOGIC
CNV
BUSY
REF/DGC
GND
237918 BD01
237918fa
8
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
