LTC2379-18
ADC TIMING CHARACTERISTICS
SYMBOL
t
SCKL
t
SSDISCK
t
HSDISCK
t
SCKCH
t
DSDO
t
HSDO
t
DSDOBUSYL
t
EN
t
DIS
PARAMETER
SCK Low Time
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
SDO Data Valid Delay from BUSY↓
Bus Enable Time After RDL↓
Bus Relinquish Time After RDL↑
(Note 11)
(Note 11)
t
SCKCH
= t
SSDISCK
+ t
DSDO
(Note 11)
C
L
= 20pF (Note 11)
C
L
= 20pF (Note 10)
C
L
= 20pF (Note 10)
(Note 11)
(Note 11)
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 4)
CONDITIONS
l
l
l
l
l
l
l
l
l
MIN
4
4
1
13.5
TYP
MAX
UNITS
ns
ns
ns
ns
9.5
1
5
16
13
ns
ns
ns
ns
ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2:
All voltage values are with respect to ground.
Note 3:
When these pin voltages are taken below ground or above REF or
OV
DD
, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OV
DD
without
latch-up.
Note 4:
V
DD
= 2.5V, OV
DD
= 2.5V, REF = 5V, V
CM
= 2.5V, f
SMPL
= 1.6MHz,
REF/DGC = V
REF
.
Note 5:
Recommended operating conditions.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 00 0000 0000 0000 0000
and 11 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8:
All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9:
f
SMPL
= 1.6MHz, I
REF
varies proportionately with sample rate.
Note 10:
Guaranteed by design, not subject to test.
Note 11:
Parameter tested and guaranteed at OV
DD
= 1.71V, OV
DD
= 2.5V
and OV
DD
= 5.25V.
Note 12:
t
SCK
of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OV
DD
0.2*OV
DD
t
DELAY
0.8*OV
DD
0.2*OV
DD
t
DELAY
0.8*OV
DD
0.2*OV
DD
50%
t
WIDTH
50%
237918 F01
Figure 1. Voltage Levels for Timing Specifications
237918fa
5
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
