LTC2978
ELECTRICAL CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating for extended periods may affect device reliability and lifetime.
Note 2:
All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the V
DD33
pin only, connect
V
PWR
and V
DD33
pins together.
Note 3:
Hysteresis in the output voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 4:
TUE(%) is defined as:
Gain Error (%) + 100 • (INL + V
OS
)/V
IN
.
Note 5:
Integral nonlinearity (INL) is defined as the deviation of a code
from a straight line passing through the actual endpoints of the transfer
curve (0V and 6V). The deviation is measured from the center of the
quantization band.
Note 6:
The time between successive ADC conversions (latency of the
ADC) for any given channel is given as: 36.9ms + (6.15ms • number of
ADC channels configured in Low Resolution mode) + (24.6ms • number of
ADC channels configured in High Resolution mode).
Note 7:
Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 8:
EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 9:
The LTC2978 will not acknowledge any PMBus commands while a
mass write operation is being executed. This includes the STORE_USER_ALL
and MFR_FAULT_LOG_STORE commands or a fault log store initiated by a
channel faulting off.
Note 10:
Maximum capacitive load, C
B
, for SCL and SDA is 400pF Data
.
and clock rise time (t
r
) and fall time (t
f
) are: (20 + 0.1 • C
B
) (ns) < t
r
< 300ns
and (20 + 0.1 • C
B
) (ns) < t
f
< 300ns. C
B
= capacitance of one bus line in pF
.
SCL and SDA external pull-up voltage, V
IO
, is 3.13V < V
IO
< 5.5V.
Note 11:
EEPROM endurance and retention will be degraded when T
J
> 85°C.
Note 12:
Output enable pins are charge pumped from V
DD33
.
Note 13:
The current sense resolution is determined by the L11 format
and the mV units of the returned value. For example a full scale value
of 170mV returns a L11 value of 0xF2A8 = 680 • 2
–2
= 170. This is the
lowest range that can represent this value without overflowing the L11
mantissa and the resolution for 1LSB in this range is 2
–2
mV = 250µV.
Each successively lower range improves resolution by cutting the LSB size
in half.
PMBUS TIMING DIAGRAM
SDA
t
f
SCL
t
HD(STA)
START
CONDITION
t
HD(DAT)
t
HIGH
t
SU(STA)
REPEATED START
CONDITION
t
SU(STO)
2978 TD
t
LOW
t
r
t
SU(DAT)
t
f
t
HD(SDA)
t
SP
t
r
t
BUF
STOP
CONDITION
START
CONDITION
2978fc
9
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
