LT1568
PI FU CTIO S
V
+
(Pins 1, 16):
The V
+
positive supply voltage pins should
be tied together and bypassed with a 0.1µF capacitor to an
adequate analog ground plane using the shortest possible
wiring.
INVA, INVB (Pins 2, 15):
Inverting Input. Each of the INV
pins is an inverting input of an op amp. Note that the INV
pins are high impedance, and are susceptible to coupling
of unintended signals. External parasitic capacitance on
the INV nodes will also affect the frequency response of
the filter sections. For these reasons, printed circuit con-
nections to the INV pins must be kept as short as possible.
SA, SB (Pins 3, 14):
Summing Pins. These pins are a
summing junction for input signals. Stray capacitance on
the SA or SB pins may cause “small” frequency errors of
the frequency response near the cutoff frequency (or
center frequency). The three external resistors for each
section should be located as close as possible to the SA or
SB pin to minimize stray capacitance (one picofarad of
stray capacitance may add up to 0.1% frequency error).
OUTA, OUTB (Pins 4, 13):
Lowpass Output. These pins
are the rail-to-rail outputs of op amps. Each output is
designed to drive a nominal net load of 400Ω and 30pF.
OUTA, OUTB (Pins 5, 12):
These pins are the inverted
versions of the OUTA and OUTB outputs respectively. Each
output is designed to drive a nominal load of 400Ω and
30pF.
GNDA (Pin 6):
GNDA serves as the common mode refer-
ence voltage for section A. It should be tied to the analog
ground plane in a dual supply system. In a single-supply
system, an internal resistor divider can be used to estab-
lish a half-supply reference point. In that case, GNDA must
be bypassed to V
–
(Pins 8, 9) by a 0.1µF capacitor.
NC (Pin 7):
This pin is not connected internally and can be
connected to ground.
V
–
(Pins 8, 9):
The V
–
negative supply voltage pins should
be tied together and bypassed to GND by a 0.1µF capacitor
in a dual-supply system. In a single-supply system, tie
these pins to the ground plane.
EN (Pin 10):
ENABLE. When the EN input goes high or is
open circuited, the LT1568 enters a shutdown state which
reduces the supply current to approximately 0.5mA
(V
S
= 5V). The OUTA, OUTB, OUTA and OUTB pins
assume high impedance states. GNDA will continue to be
biased at half-supply. If an input signal is applied to a
complete filter circuit while the LT1568 is in shutdown,
some signal will normally flow to the output through
passive components around the inactive IC.
EN is connected to V
+
through an internal pull-up resistor
of approximately 40k. This defaults the LT1568 to the
shutdown state if the EN pin is left floating. Therefore, the
user must connect the EN pin to a voltage equal to or less
than (V
+
– 2.1)V to enable the part for normal operation.
(For example, if V
+
is 5V, then to enable the part the EN pin
voltage should be 2.9V or less.)
GNDB (Pin 11):
GNDB serves as the common mode
reference voltage for section B. It should be tied to the
analog ground plane in a dual supply system. In a single-
supply system, GNDB can be tied to GNDA to set the
common mode voltage at half-supply. If it is tied to
another reference voltage, GNDB should be bypassed to
V
–
(Pins 8, 9) by a 0.1µF capacitor.
8
U
U
U
1568f
LINEAR_DIMENSIONS [ LINEAR DIMENSIONS SEMICONDUCTOR ]
