LT1374
BLOCK DIAGRA
INPUT
BIAS*
2.9V BIAS
REGULATOR
SYNC
SHUTDOWN
COMPARATOR
0.4V
SHDN
3.5µA
FOLDBACK
CURRENT
LIMIT
CLAMP
Q2
FREQUENCY
SHIFT CIRCUIT
+
–
2.38V
V
C
ERROR
AMPLIFIER
g
m
= 2000µMho
*BIAS PIN IS AVAILABLE ONLY ON THE S0-8 AND FE16 PACKAGES
Figure 1. Block Diagram
APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1374 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The fixed 5V LT1374-5 has internal divider resis-
tors and the FB pin is renamed SENSE, connected directly
to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
Please read the following if divider resistors are increased
above the suggested values.
R1
=
Table 1
R2 V
OUT
−
2
.
42
2
.
42
(
OUTPUT
VOLTAGE
(V)
3
3.3
5
6
8
10
12
15
R2
(k
Ω
)
4.99
4.99
4.99
4.99
4.99
4.99
4.99
4.99
8
+
LOCKOUT
COMPARATOR
–
U
W
W
0.01Ω
+
INTERNAL
V
CC
–
CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 20
SLOPE COMP
Σ
0.9V
BOOST
500kHz
OSCILLATOR
S
CURRENT
COMPARATOR
R
S
FLIP-FLOP
DRIVER
CIRCUITRY
+
–
–
+
R
Q1
POWER
SWITCH
V
SW
FB
2.42V
GND
1374 BD
U U
)
% ERROR AT OUTPUT
DUE TO DISCREET 1%
RESISTOR STEPS
+ 0.23
+ 0.08
+ 0.39
– 0.5
– 0.04
+ 0.83
– 0.62
+ 0.52
1374fb
R1
(NEAREST 1%)
(k
Ω
)
1.21
1.82
5.36
7.32
11.5
15.8
19.6
26.1
LINER [ LINEAR TECHNOLOGY ]
