LT1640L/LT1640H
APPLICATIONS INFORMATION
Hot Circuit Insertion
When circuit boards are inserted into a live –48V backplane,
the bypass capacitors at the input of the board’s power
module or switching power supply can draw huge tran-
sient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
The LT1640 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the V
EE
pin of the LT1640). R1 provides current fault
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and over-
voltage sensing. By ramping the gate of Q1 up at a slow
rate, the surge current charging load capacitors C3 and C4
can be limited to a safe value when the board makes
connection.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The inrush current
can be calculated with the following equation:
1640 F07b
GND
R4
562k
1%
UV = 37V
R5
9.09k
1%
R6
10k
1%
8
V
DD
3
UV
LT1640H
2
OV
V
EE
4
SENSE
5
C1
0.033µF
24V
GATE
6
R2
R3
10Ω 10k C2
5% 5% 3.3nF
100V
1640 F06a
OV = 71V
R1
0.02Ω
5%
– 48V
Q1
IRF530
Figure 6a. Inrush Control Circuitry
U
W
U
U
I
INRUSH
= (45µA • C
L
)/C2
where C
L
is the total load capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
up to a voltage roughly equal to V
EE
• C2/C
G
(Q1) before the
LT1640 could power up and actively pull the gate low. By
placing capacitor C1 parallel with the gate capacitance of
Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 should be 10 times the
value of C and R3 • C1
≈
300µs.
CONTACT
BOUNCE
Figure 6b. Inrush Control Waveforms
C3
0.1µF
100V
PWRGD
1
+
VICOR
VI-J3D-CY
C4
100µF
100V
V
IN+
GATE IN
V
IN–
V
OUT–
V
OUT+
5V
+
C5
100µF
16V
DRAIN
7
7
LINER [ LINEAR TECHNOLOGY ]
