LT1641
APPLICATIO S I FOR ATIO
Power Good Detection
The LT1641 includes a comparator for monitoring the
output voltage. The noninverting input (FB pin) is com-
pared against an internal 1.233V precision reference and
exhibits 80mV hysteresis. The comparator’s output
(PWRGD pin) is an open collector capable of operating
from a pull-up as high as 100V.
The PWRGD pin can be used to directly enable/disable a
power module with an active high enable input. Figure 14
shows how to use the PWRGD pin to control an active low
enable input power module. Signal inversion is accom-
plished by transistor Q2 and R7.
V
IN
48V
R1
294k
1%
R
S
0.01Ω
Q1
IRF530
D1
CMPZ
5248B
C1
10nF
R7
47k
5%
FB
LT1641
2
R4
4.22k
1%
3
Q2
MMBT5551LT1
R5
10Ω
5%
R6,
1k, 5%
8
V
CC
1
7
SENSE
6
GATE
UV = 37V
ON
R2
10.2k
1%
TIMER
5
GND
C2
0.68µF
GND
4
Figure 14. Active Low Enable Module
10
U
Supply Transient Protection
The LT1641 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 100V. However,
spikes above 100V may damage the part. During a short-
circuit condition, the large change in currents flowing
through the power supply traces can cause inductive
voltage spikes which could exceed 100V. To minimize the
spikes, the power trace parasitic inductance should be
minimized by using wider traces or heavier trace plating
and a 0.1µF bypass capacitor placed between V
CC
and
GND. A surge suppressor at the input can also prevent
damage from voltage surges.
R3
143k
1%
ACTIVE LOW
ENABLE MODULE
W
U
U
+
V
IN
+
C
L
220µF
ON/OFF
V
IN
–
V
OUT
+
V
OUT
V
OUT
–
PWRGD
1641 F14
LINER [ LINEAR TECHNOLOGY ]
