LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
TYPICAL PERFORMANCE CHARACTERISTICS
I
PGH
vs Temperature
62
61
60
I
PGH
(μA)
t
SS
(μs)
59
58
57
56
55
–55 –35 –15
V
PWRGD
= 0V
(MS ONLY)
220
210
200
190
180
170
160
150
–55 –35 –15
DELAY (μs)
t
SS
vs Temperature
SS PIN FLOATING,
V
SS
RAMPS FROM 0.2V TO 2V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
5 25 45 65 85 105 125
TEMPERATURE (°C)
425212 G27
t
PLLUG
and t
PHLOG
vs Temperature
t
PLLUG
t
PHLOG
5 25 45 65 85 105 125
TEMPERATURE (°C)
425212 G38
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
425212 G24
PIN FUNCTIONS
(MS/MS8)
V
IN
(Pin 1/Pin 1):
Positive Supply Input. Connect this
pin to the positive side of the supply through a dropping
resistor. A shunt regulator clamps V
IN
at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the V
IN
pin is greater than V
LKO
, overriding UV and OV. If
UV is high, OV is low and V
IN
comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp-
up. If V
IN
drops below approximately 8.2V, GATE pulls low
immediately.
PWRGD
(Pin 2/Not Available):
Power Good Status Output
(MS only). At start-up,
PWRGD
latches low if DRAIN is
below 2.385V and GATE is within 2.8V of V
IN
.
PWRGD
status is reset by UV, V
IN
(UVLO) or a circuit breaker fault
timeout. This pin is internally pulled high by a 58μA cur-
rent source.
SS (Pin 3/Pin 2):
Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the sense
resistor during the soft-start current limiting. At the begin-
ning of a start-up cycle, the SS capacitor (C
SS
) is ramped
by a 22μA (28μA for the LTC4252A) current source. The
GATE pin is held low until SS exceeds 20 • V
OS
= 0.2V.
SS is internally shunted by a 100k resistor (R
SS
) which
limits the SS pin voltage to 2.2V (50k resistor and 1.4V
for the LTC4252A). This corresponds to an analog current
limit SENSE voltage of 100mV (60mV for the LTC4252A). If
the SS capacitor is omitted, the SS pin ramps up in about
180μs. The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SENSE (Pin 4/Pin 3):
Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor R
S
con-
nected between SENSE and V
EE
, and controlled in three
steps. If SENSE exceeds V
CB
(50mV), the circuit breaker
comparator activates a (230μA + 8 • I
DRN
) TIMER pull-up
current. If SENSE exceeds V
ACL
, the analog current limit
amplifier pulls GATE down to regulate the MOSFET current
at V
ACL
/R
S
. In the event of a catastrophic short-circuit,
SENSE may overshoot. If SENSE reaches V
FCL
(200mV),
the fast current limit comparator pulls GATE low with a
strong pull-down. To disable the circuit breaker and cur-
rent limit functions, connect SENSE to V
EE
.
425212fd
9
LINER [ LINEAR TECHNOLOGY ]
