LT4356-1/LT4356-2
APPLICATIONS INFORMATION
This fixed early warning period allows the systems to per-
formnecessarybackuporhouse-keepingfunctionsbefore
voltage N-channel MOSFETs. For systems with V less
than 8V, a logic level MOSFET is required since the gate
drive can be as low as 4.5V.
CC
the power supply is cut off. After V
crosses the 1.35V
TMR
threshold, the pass transistor turns off immediately. Note
that during an overcurrent event, the timer current is not
The SOA of the MOSFET must encompass all fault condi-
tions. In normal operation the pass transistor is fully on,
dissipating very little power. But during either overvoltage
or overcurrent faults, the GATE pin is servoed to regu-
late either the output voltage or the current through the
MOSFET. Large current and high voltage drop across the
MOSFET can coexist in these cases. The SOA curves of
the MOSFET must be considered carefully along with the
selection of the fault timer capacitor.
reduced to 5μA after V
has reached 1.25V threshold,
TMR
since it would lengthen the overall fault timer period and
cause more stress on the power MOSFET.
As soon as the fault condition has disappeared, a 2μA
current starts to discharge the timer capacitor to ground.
WhenV
reachesthe0.5Vthreshold,theinternalcharge
TMR
pump starts to pull the GATE pin high, turning on the
MOSFET. The TMR pin is then actively regulated to 0.5V
until the next fault condition appears. The total cool down
timer period is given by:
Transient Stress in the MOSFET
During an overvoltage event, the LT4356 drives a series
passMOSFETtoregulatetheoutputvoltageatanacceptable
level.Theloadcircuitrymaycontinueoperatingthroughout
this interval, but only at the expense of dissipation in the
MOSFET pass device. MOSFET dissipation or stress is a
function of the input voltage waveform, regulation voltage
and load current. The MOSFET must be sized to survive
this stress.
CTMR • 0.85V
tCOOL
=
2μA
MOSFET Selection
The LT4356 drives an N-channel MOSFET to conduct the
load current. The important features of the MOSFET are
on-resistanceR
(BR)DSS
,themaximumdrain-sourcevoltage
DS(ON)
Most transient event specifications use the model shown
in Figure 3. The idealized waveform comprises a linear
V
, the threshold voltage, and the SOA.
The maximum allowable drain-source voltage must be
higher than the supply voltage. If the output is shorted
to ground or during an overvoltage event, the full supply
voltage will appear across the MOSFET.
ramp of rise time t, reaching a peak voltage of V and
r
PK
exponentially decaying back to V with a time constant
IN
of t. A common automotive transient specification has
constants of t = 10μs, V = 80V and τ = 1ms. A surge
r
PK
condition known as “load dump” has constants of t =
r
The gate drive for the MOSFET is guaranteed to be more
5ms, V = 60V and τ = 200ms.
PK
than10Vandlessthan16VforthoseapplicationswithV
CC
higher than 8V. This allows the use of standard threshold
V
PK
τ
V
IN
t
r
4356 F03
Figure 3. Prototypical Transient Waveform
4356fa
13
Linear Systems [ Linear Systems ]
