LTC1263
OPERATION
The LTC1263 uses a charge pump tripler to generate 12V
from a V
CC
of 5V. The charge pump is clocked by an
internal oscillator. The oscillator frequency is not critical
and may vary from the typical value of 300kHz. When the
oscillator output is low, C1 and C2 are each connected
between V
CC
and GND, charging them to V
CC
(see Figure
3). When the oscillator output goes high, C1 and C2 are
stacked in series with the bottom plate of C1 pulled to V
CC
(see Figure 4). The top plate of C2 is switched to charge
C
OUT
, which enables V
OUT
to rise.
V
OUT
is regulated to within 5% of 12V by an oscillator pulse
gating scheme that turns the charge pump on and off
based on the comparator results of V
OUT
and a reference
voltage. First, a resistor divider senses V
OUT
; if the output
of the divider (V
DIV
) is less than the output of a bandgap
(V
BGAP
) by the hysteresis voltage (V
HYST
) of the compara-
tor, then oscillator pulses are applied to the charge pump
to raise V
OUT
. When V
DIV
is above V
BGAP
by V
HYST
, the
V
CC
V
OUT
C
OUT
Figure 3. C1 and C2 Charge to V
CC
APPLICATIONS INFORMATION
Choice of Capacitors
The LTC1263 is tested with the capacitors shown in Figure
2. C1 and C2 are 0.47µF ceramic capacitors and C
IN
and
C
OUT
are 10µF tantalum capacitors. Refer to Table 1 if
other choices are desired.
Table 1. Recommended Capacitor Types and Values
CAPACITOR
C1, C2
C
OUT
C
IN
CERAMIC
0.47µF to 1µF
10µF (Min)
10µF (Min)
TANTALUM
10µF (Min)
10µF (Min)
ALUMINUM
10µF (Min)
10µF (Min)
Not Recommended Not Recommended
U
W
U
U
U
oscillator pulses are prevented from clocking the charge
pump. As a result, V
OUT
drops until V
DIV
is below V
BGAP
by
V
HYST
again.
To ensure proper start-up when V
OUT
is lower than V
CC
and maintain proper operation when V
OUT
is higher than
V
CC
, the gates of all internal switches are driven between
GND and the higher of either V
OUT
or V
CC
.
To reduce supply current, the LTC1263 may be put into
shutdown mode by “floating” the SHDN pin or connecting
it to V
CC
. In this mode, the bandgap, comparator, oscilla-
tor and resistor divider are switched off to reduce the
supply current to typically 0.5µA. At the same time an
internal switch shorts V
OUT
to V
CC
; V
OUT
takes 10ms (typ)
to reach 5.1V (see t
OFF
in Figure 1). When the SHDN pin
is low, the LTC1263 exits shutdown and the charge pump
operates to raise V
OUT
to 12V. V
OUT
takes 600µs (typ) to
reach the lower regulation limit of 11.4V (see t
ON
in Figure 1).
+
C1
+
C2
V
CC
+
C2
+
C1
LTC1263 • F04
LTC1263 • F03
Figure 4. C1 and C2 Stacked in Series with C1
–
Tied to V
CC
C1 and C2 should be ceramic capacitors with values in the
range of 0.47µF to 1µF. Higher values provide better load
regulation. Tantalum capacitors are not recommended as
the higher ESR of these capacitors degrades performance
at high load currents and V
CC
= 4.75V.
C
IN
and C
OUT
can be ceramic, tantalum or electrolytic
capacitors. The ESR of C
OUT
introduces steps in the V
OUT
waveform whenever the charge pump charges C
OUT
. This
tends to increase V
OUT
ripple. Ceramic or tantalum capaci-
tors are recommended for C
OUT
if minimum ripple is
5
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