LTC1474/LTC1475
APPLICATIONS INFORMATION
C
IN
and C
OUT
Selection
At higher load currents, when the inductor current is
continuous, the source current of the P-channel MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
capacitor current is given by:
I
MAX
V
OUT
V
IN
−
V
OUT
V
IN
negligible ESR. AVX and Marcon are good sources for
these capacitors.
In surface mount applications multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount configurations. In the case of tantalum, it is
critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heights ranging from 2mm to 4mm. Other capacitor types
include SANYO OS-CON, Nichicon PL series and Sprague
595D series. Consult the manufacturer for other specific
recommendations.
To avoid overheating, the output capacitor must be sized
to handle the ripple current generated by the inductor. The
worst-case ripple current in the output capacitor is given
by:
I
RMS
= I
PEAK
/ 2
Once the ESR requirement for C
OUT
has been met, the
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1474/LTC1475 circuits: V
IN
current, I
2
R
losses and catch diode losses.
1. The V
IN
current is due to two components: the DC bias
current and the internal P-channel switch gate charge
current. The DC bias current is 9µA at no load and
increases proportionally with load up to a constant
100µA during continuous mode. This bias current is so
C
IN
Required I
RMS
=
[
(
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Do not underspecify this component. An addi-
tional 0.1µF ceramic capacitor is also required on V
IN
for
high frequency decoupling.
The selection of C
OUT
is driven by the required effective
series resistance (ESR) to meet the output voltage ripple
and line regulation requirements. The output voltage ripple
during a burst cycle is dominated by the output capacitor
ESR and can be estimated from the following relation:
25mV <
∆V
OUT, RIPPLE
=
∆I
L
• ESR
where
∆I
L
≤
I
PEAK
and the lower limit of 25mV is due to the
voltage comparator hysteresis. Line regulation can also
vary with C
OUT
ESR in applications with a large input
voltage range and high peak currents.
ESR is a direct function of the volume of the capacitor.
Manufacturers such as Nichicon, AVX and Sprague should
be considered for high performance capacitors. The
OS-CON semiconductor dielectric capacitor available from
SANYO has the lowest ESR for its size at a somewhat
higher price. Typically, once the ESR requirement is satis-
fied, the capacitance is adequate for filtering. For lower
current applications with peak currents less than 50mA,
10µF ceramic capacitors provide adequate filtering and
are a good choice due to their small size and almost
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