LTC1701
APPLICATIO S I FOR ATIO
Soft-start can be implemented by ramping the voltage on
I
TH
/RUN during start-up as shown in Figure 3(c). As the
voltage on I
TH
/RUN ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
During normal operation the voltage on the I
TH
/RUN pin
will vary from 1.25V to 2.25V depending on the load
current. Pulling the I
TH
/RUN pin below 0.8V puts the
LTC1701 into a low quiescent current shutdown mode
(I
Q
< 1µA). This pin can be driven directly from logic as
shown in Figures 3(a) and 3(b).
3.3V OR 5V
D1
C
C
R
C
C
C
R
C
I
TH
/RUN
I
TH
/RUN
(a)
I
TH
/RUN
R1
D1
C
C
C1
R
C
(c)
Figure 3. I
TH
/RUN Pin Interfacing
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and what change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC1701 circuits: 1) LTC1701 V
IN
current,
2) switching losses, 3) I
2
R losses, 4) Schottky diode
losses.
8
U
1) The V
IN
current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V
IN
current results in a small (< 0.1%)
loss that increases with V
IN
, even at no load.
2) The switching current is the sum of the internal MOSFET
driver and control currents. The MOSFET driver current
results from switching the gate capacitance of the power
MOSFET. Each time a MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from V
IN
to ground. The resulting dQ/dt is a current out of V
IN
that
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
= f • Q
P
, where Q
P
is the gate
charge of the internal MOSFET switch.
3) I
2
R Losses are predicted from the DC resistances of the
MOSFET and inductor. In continuous mode the average
output current flows through L, but is “chopped” between
the topside internal MOSFET and the Schottky diode. At
low supply voltages where the switch on-resistance is
higher and the switch is on for longer periods due to the
higher duty cycle, the switch losses will dominate. Using
a larger inductance helps minimize these switch losses. At
high supply voltages, these losses are proportional to the
load. I
2
R losses cause the efficiency to drop at high output
currents.
4) The Schottky diode is a major source of power loss at
high currents and gets worse at low output voltages. The
diode loss is calculated by multiplying the forward voltage
drop times the diode duty cycle multiplied by the load
current.
Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important to
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.
(b)
1701 F03
W
U
U
LINER [ LINEAR TECHNOLOGY ]
