LTC3206
OPERATIO
The 1.5x step-up charge pump uses a patented constant
frequency architecture to combine the best efficiency with
the maximum available power at the lowest noise level.
The charge pump of the LTC3206 can be forced to come
on even if no LEDs are programmed for current. Setting bit
A3 in the I
2
C serial port forces the charge pump on (see
Figure 3).
Soft-Start
To prevent excessive inrush current and supply droop
when switching into step-up mode, the LTC3206 employs
a soft-start feature on its charge pump. The current
available to the CPO pin is increased linearly over a period
of about 400µs.
Charge Pump Strength
When the LTC3206 operates in 1.5x boost mode, the
charge pump can be modeled as a Thevenin-equivalent
circuit to determine the amount of current available from
the effective input voltage, 1.5V
IN
and the effective open-
loop output resistance, R
OL
(Figure 1).
R
OL
is dependent on a number of factors including the
switching term, 1/(2f
OSC
• C
FLY
), internal switch resis-
tances and the non-overlap period of the switching circuit.
However, for a given R
OL
, the amount of current available
will be directly proportional to the advantage voltage 1.5V
IN
– V
CPO
. Consider the example of driving white LEDs from
a 3.1V supply. If the LED forward voltage is 3.8V and the
current sources require 100mV, the advantage voltage is
3.1V • 1.5 – 3.8V – 0.1V or 750mV. Notice that if the input
voltage is raised to 3.2V, the advantage voltage jumps to
900mV—a 20% improvement in available strength.
From Figure 1, the available current is given by:
I
OUT
=
1.5V
IN
– V
CPO
R
OL
R
OL
OUTPUT RESISTANCE (Ω)
Figure 1. Equivalent Open-Loop Circuit
3206f
U
Typical values of R
OL
as a function of temperature are
shown in Figure 2.
2.50
V
IN
= 3V
V
CPO
= 4.2V
C
IN
= C
CPO
= C
FLY1
= C
FLY2
= 1.6µF
2.25
2.00
1.75
1.50
–40
–15
10
35
TEMPERATURE (°C)
60
85
3206 F02
Figure 2. Typical R
OL
vs Temperature
I
2
C Interface
The LTC3206 communicates with a host (master) using
the standard I
2
C 2-wire interface. The Timing Diagram
(Figure 4) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines. The LTC3206 is a receive-only
(slave) device.
Bus Speed
The I
2
C port is designed to be operated at speeds of up to
400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
2
C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
START and STOP Conditions
A bus-master signals the beginning of a communication to
a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high. When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I
2
C device.
+
CPO
+
–
1.5V
IN
–
3206 F01
7
LINER [ LINEAR TECHNOLOGY ]
