LTC3717
Wide Operating Range,
No R
SENSE
TM
Step-Down Controller
for DDR/QDR Memory Termination
FEATURES
s
s
DESCRIPTIO
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
V
OUT
= 1/2 V
IN
(Supply Splitter)
Adjustable and Symmetrical Sink/Source
Current Limit up to 20A
±0.65%
Output Voltage Accuracy
Up to 97% Efficiency
No Sense Resistor Required
Ultrafast Transient Response
True Current Mode Control
2% to 90% Duty Cycle at 200kHz
t
ON(MIN)
≤
100ns
Stable with Ceramic C
OUT
Dual N-Channel MOSFET Synchronous Drive
Power Good Output Voltage Monitor
Wide V
CC
Range: 4V to 36V
Adjustable Switching Frequency up to 1.5MHz
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Available in a 16-Pin Narrow SSOP Package
The LTC
®
3717 is a synchronous step-down switching
regulator controller for double data rate (DDR) and Quad
Data Rate
TM
(QDR
TM
) memory termination. The controller
uses a valley current control architecture to deliver very
low duty cycles without requiring a sense resistor. Oper-
ating frequency is selected by an external resistor and is
compensated for variations in V
IN
.
Forced continuous operation reduces noise and RF inter-
ference. Output voltage is internally set to half of V
REF
,
which is user programmable.
Fault protection is provided by an output overvoltage
comparator and optional short-circuit shutdown timer.
Soft-start capability for supply sequencing is accom-
plished using an external timing capacitor. The regulator
current limit level is symmetrical and user programmable.
Wide supply range allows operation from 4V to 36V at the
V
CC
input.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No R
SENSE
is a trademark of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
APPLICATIO S
s
s
s
Bus Termination: DDR and QDR Memory, SSTL,
HSTL, ...
Notebook Computers, Desktop Servers
Tracking Power Supply
TYPICAL APPLICATIO
V
CC
5V TO 28V
1µF
V
CC
I
ON
V
REF
RUN/SS
C
C
470pF
C
SS
0.1µF
I
TH
R
C
20k
SGND
LTC3717
INTV
CC
BG
TG
SW
BOOST
R
ON
715k
V
DD
= 2.5V
M1
Si7840DP
C
B
0.22µF
D
B
CMDSH-3
M2
Si7840DP
C
VCC
4.7µF
D2
B320A
+
V
IN
2.5V TO 5.5V
C
IN
150µF
6.3V
×2
V
OUT
1.25V
C
OUT
±10A
180µF
4V
×2
EFFICIENCY (%)
L1
0.68µH
+
+
D1
B320A
PGOOD
PGND
V
FB
3717 F01a
Figure 1. High Efficiency DDR Memory Termination Supply
sn3717 3717fs
U
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
LOAD CURRENT (A)
12
14
V
IN
= 5V
V
IN
= 2.5V
V
OUT
= 1.25V
3717 F01b
U
U
1
LINER [ LINEAR TECHNOLOGY ]
