L10C11
DEVICES INCORPORATED
4/8-bit Variable Length Shift Register
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of
I
OH
and
I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the
t
DIS
test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
2. The products described by this speci-
fication include internal circuitry de-
signedto protect the chipfrom damaging
substrate injection currents and accumu-
12. These parameters are only tested at
lations of static charge. Nevertheless,
the high temperature extreme, which is
conventional precautions should be ob-
the worst case for leakage current.
served during storage, handling, and use
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
of these circuits in order to avoid expo- This device has high-speed outputs ca-
sure to excessive electrical stress values. pable of large instantaneous current
pulses and fast turn-on/turn-off times.
3. This device provides hard clamping of As a result, care must be exercised in the
S1
transient undershoot and overshoot. In- testing of this device. The following
DUT
I
OL
put levels below ground or above
V
CC
measures are recommended:
V
TH
C
L
will be clamped beginning at –0.6 V and
I
OH
V
CC
+ 0.6 V. The device can withstand a. A 0.1 µF ceramic capacitor should be
indefinite operation with inputs in the installed between
V
CC
and Ground
range of –0.5 V to +7.0 V. Device opera- leads as close to the Device Under Test
F
IGURE
B. T
HRESHOLD
L
EVELS
tion will not be adversely affected, how- (DUT) as possible. Similar capacitors
t
ENA
t
DIS
ever, input current levels will be well in should be installed between device
V
CC
OE
1.5 V
1.5 V
excess of 100 mA.
and the tester common, and device
ground and tester common.
3.5V Vth
0
Z
4. Actual test conditions may vary from
1.5 V
V
OL
*
0.2 V
Z
0
those designated but operation is guar- b. Ground and
V
CC
supply planes
1
Z
anteed as specified.
must be brought directly to the DUT
0.2 V
V
OH
*
1.5 V
0V Vth
Z
1
socket or contactor fingers.
5. Supply current for a given application
V
OL
* Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
V
OH
* Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
can be accurately approximated by:
c. Input voltages should be adjusted to
compensate for inductive ground and
V
CC
NCV
2
F
noise to maintain required DUT input
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
6. Tested with all outputs changing ev- specified as a minimum since the exter-
ery cycle and no load, at a 5 MHz clock nal system must supply at least that
much time to meet the worst-case re-
rate.
quirements of all parts. Responses from
7. Tested with all inputs within 0.1 V of the internal circuitry are specified from
V
CC
or Ground, no load.
the point of view of the device. Output
8. These parameters are guaranteed delay, for example, is specified as a
maximum since worst-case operation of
but not 100% tested.
any device always provides data within
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
Pipeline Registers
4
03/27/2000–LDS.11-L
LOGIC [ LOGIC DEVICES INCORPORATED ]
