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L2330QC25 参数 Datasheet PDF下载

L2330QC25图片预览
型号: L2330QC25
PDF下载: 下载PDF文件 查看货源
内容描述: 协调变压器 [Coordinate Transformer]
分类和应用: 变压器
文件页数/大小: 14 页 / 297 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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L2330
DEVICES INCORPORATED
Coordinate Transformer
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damag-
sources of
I
OH
and
I
OL
respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Never- used. Parasitic capacitance is 30 pF
theless, conventional precautions minimum, and may be distributed.
should be observed during storage,
handling, and use of these circuits in This device has high-speed outputs ca-
order to avoid exposure to excessive pable of large instantaneous current
electrical stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping testing of this device. The following
of transient undershoot and overshoot. measures are recommended:
Input levels below ground or above
V
CC
will be clamped beginning at – a. A 0.1 µF ceramic capacitor should be
0.6 V and
V
CC
+ 0.6 V. The device can installed between
V
CC
and Ground
withstand indefinite operation with in- leads as close to the Device Under Test
puts in the range of –0.5 V to +7.0 V. (DUT) as possible. Similar capacitors
Device operation will not be adversely should be installed between device
V
CC
affected, however, input current levels and the tester common, and device
ground and tester common.
will be well in excess of 100 mA.
4. Actual test conditions may vary b. Ground and
V
CC
supply planes
from those designated but operation is must be brought directly to the DUT
guaranteed as specified.
socket or contactor fingers.
5. Supply current for a given application c. Input voltages should be adjusted to
can be accurately approximated by:
compensate for inductive ground and
V
CC
noise to maintain required DUT input
NCV
2
F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the
t
DIS
test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
DUT
S1
I
OL
C
L
I
OH
V
TH
F
IGURE
B. T
HRESHOLD
L
EVELS
t
ENA
OE
Z
0
1.5 V
1.5 V
1.5 V
t
DIS
3.5V Vth
V
OL
*
0.2 V
0
1
Z
Z
1.5 V
V
OH
*
0.2 V
Z
1
0V Vth
V
OL
* Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
V
OH
* Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
Special Arithmetic Functions
12
09/27/2001–LDS.2330-E