L29C525
DEVICES INCORPORATED
Dual Pipeline Register
L29C525
DEVICES INCORPORATED
Dual Pipeline Register
DESCRIPTION
The
L29C525
is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration imple-
mented is determined by the instruc-
tion code (I
1-0
) as shown in Table 2.
The I
1-0
instruction code controls the
internal routing of data and loading of
each register. For instruction I
1-0
= 00
(Push A and B), data applied at the
D
7-0
inputs is latched into register A0
on the rising edge of CLK. The
contents of A0 simultaneously move
to register A1, A1 moves to A2, and so
on. The contents of register A7 are
wrapped back to register B0. The
registers on the B side are similarly
shifted, with the contents of register
B7 lost.
Instruction I
1-0
= 01 (Push B) acts
similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register B0, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction I
1-0
= 10 (Push
A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.
Instruction I
1-0
= 11 (Hold) causes no
internal data movement. It is equiva-
lent to preventing the application of a
clock edge to any internal register.
The contents of any of the registers is
selectable at the output through the
use of the S
3-0
control inputs. The
independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S
3-0
controls
is given in Table 3.
FEATURES
u
u
u
u
u
u
u
u
Dual 8-Deep Pipeline Register
Configurable to Single 16-Deep
Low Power CMOS Technology
Replaces AMD Am29525
Load, Shift, and Hold Instructions
Separate Data In and Data Out Pins
Three-State Outputs
Package Styles Available:
• 28-pin Plastic DIP
• 28-pin Plastic LCC, J-Lead
L29C525 B
LOCK
D
IAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
REGISTER A0
REGISTER A1
REGISTER A2
REGISTER A3
REGISTER A4
REGISTER A5
REGISTER A6
D
7-0
8
I
1-0
2
CLK
REGISTER A7
MUX
Y
7-0
8
OE
REGISTER B0
REGISTER B1
REGISTER B2
REGISTER B3
REGISTER B4
REGISTER B5
REGISTER B6
REGISTER B7
MUX
S
3-0
4
Pipeline Registers
1
03/23/2000–LDS.29C525-G
LOGIC [ LOGIC DEVICES INCORPORATED ]
