PRELIMINARY INFORMATION
L7C108
L7C109
128K x 8 Static RAM
FEATURES
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
and Single or Dual Chip Selects
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
Data Retention at 2 V for Battery
Backup Operation
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
Package Styles Available:
32-pin Ceramic 400mil DIP D12
32-pin Ceramic LCC K11
32-pin Ceramic SO
1
32-pin uad Ceramic LCC KA1
Pin Configuration
32-pin Ceramic DIP
32-pin Ceramic SOJ
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
32-pin Quad CLCC
A
2
A
1
A
0
NC
V
CC
A
16
NC
32-pin Ceramic LCC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
5
6
7
8
9
10
11
12
13
Top
View
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
DQ
8
14 15 16 17 18 19 20
OVERVIEW
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
Chip Enables one active-low . These
devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
-L Version at 15 ns. Data may be
retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
chronous unclocked operation with
matching access and cycle times. The
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
Memory locations are specified on
address pins A
0
through A
16
. For the
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE
1
and OE
LOW while WE remains HIGH. For the
L7C109, CE
1
and OE must be LOW
while CE
2
and WE are HIGH.The data in
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE
1
or OE is
HIGH, or CE
2
L7C109 or WE is LOW.
Writing to an addressed location is
accomplished when the active-low CE
1
and WE inputs are both LOW, and CE
2
L7C109 is HIGH. Any of these signals
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
DQ
2
DQ
3
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
LOGIC Devices Incorporated
www.logicdevices.com
1
1M Static RAMs
Aug 11, 2010 LDS-L7C108/9-F
LOGIC [ LOGIC DEVICES INCORPORATED ]
