L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
“final” read cycle but inhibiting
further read operations with the data
outputs remaining in a high imped-
ance state. Once a valid write operat-
ing has been accomplished, the Empty
Flag (EF) will go HIGH after
tWHEH
and a valid read can then begin.
When the FIFO is empty, the internal
read pointer is blocked from R so
external changes in R will not affect
the FIFO.
FL/RT — First Load/Retransmit
Outputs
FF — Full Flag
The Full Flag (FF) will go LOW,
inhibiting further write operations,
indicating that the device is full. If the
read pointer is not moved after Reset
(RS), the Full Flag (FF) will go LOW
after 512 writes for the
L8C201,
1024
writes for the
L8C202,
2048 writes for
the
L8C203,
and 4096 writes for the
L8C204.
EF — Empty Flag
SIGNAL DEFINITIONS
Inputs
RS — Reset
Reset is accomplished whenever the
Reset (RS) input is taken to a LOW
state. During reset, both internal read
and write pointers are set to the first
location. A reset is required after
power-up before a write operation can
take place. Both the Read Enable (R)
and Write Enable (W) inputs must be
in the HIGH state during the window
shown (i.e.,
tWHSH
before the rising
edge of RS) and should not change
until
tSHWL
after the rising edge of
RS. Hall-Full Flag (HF) will be reset to
high after Reset (RS).
W — Write Enable
A write cycle is initiated on the falling
edge of this input if the Full Flag (FF)
is not set. Data setup and hold time
must be adhered to with respect to the
rising edge of the Write Enable (W).
Data is stored in the RAM array
sequentially and independently of any
on-going read operation.
To prevent data overflow, the Full
Flag (FF) will go LOW, inhibiting
further write operations. Upon the
completion of a valid read operation,
the Full Flag (FF) will go HIGH after
tRHFH,
allowing a valid write to
begin. When the FIFO is full, the
internal write pointer is blocked from
W, so external changes in W will not
affect the FIFO when it is full.
R — Read Enable
This is a dual-purpose input. In the
Depth Expansion Mode, this pin is
grounded to indicate that it is the first
loaded (see Operating Modes). In the
Single Device Mode, this pin acts as
the retransmit input. The Single
Device Mode is initiated by grounding
the Expansion In (XI).
The FIFOs can be made to retransmit
data when the Retransmit Enable
control (RT) input is pulsed LOW. A
retransmit operation will set the
internal read pointer to the first location
and will not affect the write pointer.
Read Enable (R) and Write Enable (W)
must be in the HIGH state during
retransmit. This feature is useful when
less than the full memory has been
written between resets. Retransmit will
affect the Half-Full Flag (HF), depend-
ing on the relative locations of the read
and write pointers. The retransmit
feature is not compatible with the
Depth Expansion Mode.
XI — Expansion In
BS
O
D
8-0
— Data Input
2
A read cycle is initiated on the falling
edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The
data is accessed on a First-In/First-
Out basis, independent of any ongo-
ing write operation. After Read
Enable (R) goes HIGH, the Data
Outputs (D
8-0
) will return to a high
impedance condition until the next
read operation. When all the data has
been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the
O
This input is a dual-purpose pin.
Expansion In (XI) is grounded to
indicate an operation in the single
device mode. Expansion In (XI) is
connected to Expansion Out (XO) of
the previous device in the Depth
Expansion or Daisy Chain Mode.
Data input signals for 9-bit wide data.
Data has setup and hold time require-
ments with respect to the rising edge
of W.
LE
TE
Q
8-0
— Data Output
The Empty Flag (EF) will go LOW,
inhibiting further read operations,
when the read pointer is equal to the
write pointer, indicating that the
device is empty.
XO/HF — Expansion Out/Half-Full Flag
This is a dual-purpose output. In the
Single Device Mode, when Expansion
In (XI) is grounded, this output acts as
an indication of a half-full memory.
After half of the memory is filled and
at the falling edge of the next write
operation, the Half-Full Flag (HF) will
be set to LOW and will remain set
until the difference between the write
pointer and read pointer is less than or
equal to one-half of the total memory
of the device. The Half-Full Flag (HF)
is then deasserted by the rising edge
of the read operation.
In the Depth Expansion Mode,
Expansion In (XI) is connected to
Expansion Out (XO) of the previous
device. This output acts as a signal to
the next device in the daisy chain by
providing a pulse to the next device
when the previous device reaches the
last location of memory.
Data outputs for 9-bit wide data. This
data is in a high impedance condition
whenever Read Enable (R) is in a
HIGH state or the device is empty.
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
LOGIC [ LOGIC DEVICES INCORPORATED ]
