LF3321
Horizontal Digital Image Filter
DEVICES INCORPORATED
Improved Performance
Functional Description
Figure 5. I/D Register Data Paths
DATA
REVERSAL
DATA
REVERSAL
DATA
REVERSAL
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
1-16
Delay Stage N
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
A
ALU
B
1-16
Delay Stage N 1
A
ALU
B
COEF 7
COEF 6
COEF 7
2
COEF 6
COEF 7
2
COEF 6
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
When interleaved data is fed through the device and an even tap filter is desired, the filter should be
configured for an even number of taps and the I/D Register length should match the number of data sets
interleaved together. When interleaved data is fed through the device and an odd tap filter is desired, the
filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration Register 1 and Configuration Register
3 configures Filters A and B respectively for Odd-Tap Interleave Mode. When the filter is configured for
Odd-Tap Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the
first I/D Register in the reverse data path.
When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is
structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in
the forward data path. In order to achieve the correct result, the user must divide the coefficient by two.
Data Reversal
Data reversal circuitry is placed after the multiplexers which route data from the forward data path to the
reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to
be properly aligned at the inputs of the ALUs.
Figure 6. Data Reversal
LOGIC Devices Incorporated
5
Video Imaging Products
Feb 5, 2003 LDS.3321-A
LOGIC [ LOGIC DEVICES INCORPORATED ]
