LMA1010/2010
DEVICES INCORPORATED
16 x 16-bit Multiplier-Accumulator
LMA1010/2010
DEVICES INCORPORATED
16 x 16-bit Multiplier-Accumulator
DESCRIPTION
TC, ACC, and SUB controls are latched
on the rising edge of the logical OR of
CLK A and CLK B. TC specifies the
input as two’s complement
(TC HIGH) or unsigned magnitude
(TC LOW). RND, when HIGH, adds ‘1’
to the most significant bit position of
the least significant half of the product.
Subsequent truncation of the 16 least
The LMA1010 and LMA2010 produce
significant bits produces a result
the 32-bit product of two 16-bit numbers.
correctly rounded to 16-bit preci-
The results of a series of multiplications
sion.
may be accumulated to form the sum of
products. Accumulation is performed to ACC and SUB control accumulator
35-bit precision with the multiplier prod- operation. ACC HIGH results in
addition of the multiplier product and
uct sign extended as appropriate.
the accumulator contents, with the result
Data present at the A and B input regis- stored in the accumulator register on the
ters is latched on the rising edges of rising edge of CLK R. ACC and SUB
CLK A and CLK B respectively. RND, HIGH results in subtraction of the
accumulator contents from the
multiplier product, with the result stored
B
15-0
in the accumulator register. With ACC
A
15-0
R
15-0
16
LOW and SUB LOW, no accumulation
16
occurs and the next product is loaded
A REGISTER
B REGISTER
directly into the accumulator register.
ACC LOW and SUB HIGH is undefined.
The
LMA1010
and
LMA2010
are
high-speed, low power 16-bit
multiplier-accumulators. The LMA1010
and LMA2010 are functionally identical;
they differ only in packaging. Full mili-
tary ambient temperature range opera-
tion is achieved with advanced CMOS
technology.
The LMA1010/2010 output register
(accumulator register) is divided into
three independently controlled sec-
tions. The least significant result
(LSR) and most significant result
(MSR) registers are 16 bits in length.
The extended result register (XTR) is
3 bits long. The output signals R
15-0
and input signals B
15-0
share the same
bidirectional pins.
Each output register has an indepen-
dent output enable control. In addition
to providing three-state control of the
output buffers, when OEX, OEM, or OEL
are HIGH and PREL is HIGH, data can be
preloaded via the bidirectional output
pins into the respective output registers.
Data present on the output pins is
latched on the rising edge of CLK R. The
interrelation of PREL and the enable
controls is summarized in Table 1.
FEATURES
u
20 ns Multiply-Accumulate Time
u
Replaces Fairchild TMC2210,
Cypress CY7C510, IDT 7210L,
and AMD Am29510
u
Two’s Complement or Unsigned
Operands
u
Accumulator Performs Preload,
Accumulate, and Subtract
u
Three-State Outputs
u
68-pin PLCC, J-Lead
LMA1010/2010 B
LOCK
D
IAGRAM
CLK A
CLK B
TC
ACC
SUB
REGISTER
RND
32
R
R + A
R – A
A
35
OEX
OEM
OEL
PREL
3
OEX
OEM
OEL
PRELOAD
CONTROL
LOGIC
3
LEX
LEM
LEL
PASS R
LEX
35
3
LEM
16
LEL
16
CLK R
ACCUMULATOR REGISTER
OEX
3
R
34-32
OEM
16
R
31-16
OEL
16
Multiplier-Accumulators
1
08/16/2000–LDS.10/2010-P
LOGIC [ LOGIC DEVICES INCORPORATED ]
