LMU217
DEVICES INCORPORATED
16 x 16-bit Parallel Multiplier
LMU217
DEVICES INCORPORATED
16 x 16-bit Parallel multiplier
DESCRIPTION
The
LMU217
is a high-speed, low RND is loaded on the rising edge of
power 16-bit parallel multiplier.
CLK, provided either ENA or ENB are
LOW. RND, when HIGH, adds ‘1’ to
The LMU217 produces the 32-bit prod-
the most significant bit position of the
uct of two 16-bit numbers. Data present
least significant half of the product.
at the A inputs, along with the TCA
Subsequent truncation of the 16 least
control bit, is loaded into the A register
significant bits produces a result
on the rising edge of CLK. B data and
correctly rounded to 16-bit precision.
the TCB control bit are similarly
loaded. Loading of the A and B At the output, the Right Shift control
registers is controlled by the ENA and (RS) selects either of two output formats.
ENB controls. When HIGH, these con- RS LOW produces a 31-bit product
trols prevent application of the clock to with a copy of the sign bit inserted in the
the respective register. The TCA and MSB postion of the least significant half.
TCB controls specify the operands as RS HIGH gives a full 32-bit product. Two
two’s complement when HIGH, or 16-bit output registers are provided to
unsigned magnitude when LOW.
hold the most and least significant
halves of the result (MSP and LSP) as
defined by RS. These registers are
loaded on the rising edge of CLK, subject
to the ENR control. When ENR is
B
15-0
/
HIGH, clocking of the result registers is
R
15-0
prevented.
A
15-0
TCB
16
A REGISTER
16
B REGISTER
FEATURES
u
25 ns Worst-Case Multiply Time
u
Low Power CMOS Technology
u
Replaces Cypress CY7C517,
IDT 7217L, and AMD Am29517
u
Single Clock Architecture with
Register Enables
u
Two’s Complement, Unsigned, or
Mixed Operands
u
Three-State Outputs
u
68-pin PLCC, J-Lead
LMU217 B
LOCK
D
IAGRAM
TCA
CLK
ENA
ENB
For asynchronous output, these registers
may be made transparent by setting the
feed through control (FT) HIGH and
ENR LOW.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP outputs
to be driven by the most significant half
of the result. MSPSEL HIGH routes the
least significant half of the result to the
MSP pins. In addition, the LSP is
available via the B port through a sepa-
rate three-state buffer.
RND
REGISTER
32
RS
FORMAT ADJUST
16
FT
ENR
RESULT
16
REGISTER
MSPSEL
OEM
16
R
31-16
16
OEL
Multipliers
1
08/16/2000–LDS.217-H
LOGIC [ LOGIC DEVICES INCORPORATED ]
