LSI/CSI
UL
®
LS7055
LS7056
(631) 271-0400 FAX (631) 271-0405
January 2003
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
6 DECADE PREDETERMINING UP/DOWN COUNTER
FEATURES:
• +4.75V to +15V (Vss - V
DD
)
• Preset, Presignal and Mainsignal Store
• DC to 250kHz Count Frequency
• Fully Synchronous Operation
Three Comparators with Output Flags
Automatic or Manual Preset/Reset Control
• Thumbwheel Interface for Storage Selects
• Prescale on Count Input Selectable
• Count Inhibit
• Up/Down Control
• Scan Rate up to 150kHz
• Scan Oscillator has Override Capability
• Blanking Override for Decimal Point Operaton
• Multiplexed 7 Segment and BCD Data Output
• Output latches
• Reset
• Hysteresis on Count Input
• CMOS Type Noise Immunity on all other inputs
• LS7055, LS7056 (DIP) - See Figure 1
DESCRIPTION:
The LS7055/LS7056 is a MOS synchronous 6 decade Up/Down
counter. The circuit includes storages and comparators, zero de-
tect, automatic presetting and resetting, output latches, multi-
plexed output BCD and seven segment data. Thumbwheel
switches can be used to provide BCD data to the storage net-
works in the circuit.
COUNT
(Pin 40)
Counter operates at speeds up to 250kHz and advances on the
positive edge of the input count pulse.
UP/DOWN
(Pin 39)
Counter operates in up or down mode. A high input causes the
counter to operate in the up mode while a low input causes it to
operate in the down mode.
COUNT INHIBIT
(Pin 1)
A high input inhibits counting and the counter remains at its last
count. A low input enables counting.
DATA TRANSFER INPUT
(Pin 37)
A high input allows the seven segment display and BCD data to
follow the count (the internal latches become transparent). A low
input prevents updating of the latches as the count advances and
the seven segment display and BCD data outputs remain fixed.
RESET
(Pin 4)
A high input resets and holds all counter stages at zero. A low
input allows counter operation.
PIN ASSIGNMENT - TOP VIEW
COUNT INHIBIT INPUT
DIVIDE CONTROL INPUT 1
DIVIDE CONTROL INPUT 2
RESET INPUT
1
2
3
4
40
39
38
37
36
35
34
33
LSI
COUNT INPUT
UP/DOWN INPUT
ZERO DETECT OUTPUT
DATA TRANSFER INPUT
PRESIGNAL OUTPUT
B1
B2
B4
B8
BLANKING OVERRIDE
g
f
e
d
c
b
a
SCAN OSCILLATOR INPUT
MSD
LSD+4
DIGIT
SELECT
OUTPUTS
SEGMENT
OUTPUTS
BCD
DATA
OUTPUTS
INHIBIT INTERNAL RESET INPUT 5
INHIBIT INTERNAL PRESET INPUT 6
PRESET INPUT
V
DD
(-V)
MAIN SIGNAL OUTPUT
7
8
9
LS7055
32
31
30
29
28
27
26
25
24
23
22
21
B1 10
BCD
DATA
INPUTS
B4 11
B2 12
B8 13
V
SS
(+V)
14
*
SELECT STORAGE INPUT 1 15
SELECT STORAGE INPUT 2 16
LSD 17
DIGIT
SELECT
OUTPUTS
L S D + 1 18
L S D + 2 19
L S D + 3 20
FIGURE 1
*
OPTIONAL CHOICE-LAMP TEST (SPECIFY LS7056)
INHIBIT INTERNAL RESET
(Pin 5)
A high input prevents the automatic reset of the counter to zero when
in the up mode and when the counter reaches the number in the
main signal store.
PRESET
(Pin 7)
A high level presets the BCD counter to the number set in the preset
store. A low input allows counter operation.
INHIBIT INTERNAL PRESET
(Pin 6)
A high input prevents the automatic preset of the counter to the
number set in preset store when in the down mode and the counter
reaches zero.
SELECT STORAGE OF DATA INPUTS
(Pins 15, 16)
Two inputs which allow BCD data to be stored in either the preset,
presignal or main signal store. The proper method for loading the
stores is depicted in Figure 4.
PIN 15
0
1
0
1
PIN16
0
0
1
1
STORAGE
No Selection
Presignal
Main Signal
Preset
7055-012703-1
LSI [ LSI COMPUTER SYSTEMS ]
