BCD DATA INPUTS
(Pins 10, 11, 12, 13)
Four inputs containing BCD data which are applied to either the
preset, presignal or main signal stores one decade at a time. This
data can be provided by a set of thumbwheel switches which are
driven by the digit select outputs. Referring to Figure 4, the BCD
data inputs have built in pull down resistors (typically 51k Ohms).
DIVIDE CONTROL
(Pin 2, Pin 3)
Two inputs for selection to divide the count input by either 5, 6 or 1.
PIN 2
0
1
1
PIN 3
0
0
1
LAMP TEST
(LS7056 only) (Pin 31)
A high input will cause the seven segment outputs to provide all 8's
to a display (BCD outputs are not affected).
ZERO DETECT OUTPUT
(Pin 38)
A high output occurs whenever the counter is at zero. In the auto-
matic mode and with the Up/Down input in the down mode, the
counter presets to the number in the preset store and the zero
detect output is typically a 1.5 µs pulse. In the manual mode
(inhibit internal preset is high), the counter remains at zero until a
preset or a count input pulse is applied.
DIGIT SELECT OUTPUTS
(Pins 17, 18, 19, 20, 21, 22)
Six positive outputs for digit identification. The outputs occur
sequentially going from MSD to LSD and can be applied directly to
thumbwheel switches. They must be buffered before being applied
to the seven segment displays either by a CMOS or transistor buf-
fer as shown in Figure 5. Figure 3 indicates the timing relationship
between the digit select outputs and the BCD data outputs.
SEVEN SEGMENT OUTPUTS
(Pins 24, 25, 26, 27, 28, 29, 30)
Capable of sourcing current into the base of a common emitter
NPN transistor for interfacing to a seven segment display. Small
displays needing an average current of 0.5 mA can be interfaced
to the circuit without external transistors. A typcial example of a
12V circuit is shown in Figure 5.
BCD OUTPUTS
(Pins 32, 33, 34, 35)
Four outputs corresponding to the BCD data stored in the latches.
The outputs can be demultiplexed using the circuitry shown in Fig-
ure 4. As can be seen from the timing diagram of Figure 3, the
BCD data output and seven segment outputs are completely
stable during the positive digit select outputs.
POWER-ON-RESET
An external RC network applied to the reset input as shown in Fig-
ure 4 can be used to reset the counter to zero upon application of
power. The preset input must be held low at this time. The RC time
constant should be larger than the power supply rise time. For ex-
ample, a 100kΩ resistor and a 0.1µF capacitor could be used if the
power supply rise time was 5 ms.
POWER SUPPLIES
The circuit operates over the range of +4.75V to +15V. At +4.75V,
the inputs are TTL and CMOS compatible (external pull-up re-
sistors must be provided on any input which does not pull up to
Vss) when using TTL inputs. At +15V, inputs are CMOS compat-
ible. All outputs are CMOS compatible from +4.75V to +15V.
Divide by 5
Divide by 6
Divide by 1
MAIN SIGNAL OUTPUT
(Pin 9)
An internal comparator provides a high level output when the num-
ber set into the main signal store is reached by the counter. In the
automatic mode and with the Up/Down control in the up position,
the counter is reset to zero and the main signal output is typically a
2.5 µs wide pulse. In the manual mode (inhibit internal reset is high)
the output remains high until the next count input or a reset is ap-
plied.
PRESIGNAL OUTPUT
(Pin 36)
The presignal comparator provides a high level output when the
number set into the presignal storage is reached. The output re-
mains high until the next count input or a reset or preset is applied.
SCAN CLOCK INPUT
(Pin 23)
A DC to 150kHz oscillator input port for driving the internal scan
counter is provided. Up to 150kHz may be used when de-
multiplexilng BCD data using the digit select outputs. The fre-
quency of the oscillator is determined by an external RC network as
shown in Figure 4. Table 1 indicates several frequencies and their
associated RC networks. The oscillator can be overridden using an
external driver. Table 2 indicates the external drive requriements.
When displaying, leading zero blanking and unblanking on LSD is
provided.
BLANKING OVERRIDE
(LS7055 only) (Pin 31)
On circuits with this option, unblanking can be made to occur on
any digit by connecting that digit select output to the unblanking in-
put. Since the input has an internal pull down resistor, it can be left
floating when not in use.
TABLE 1
Typical resistor/capacitor values for the scan oscillator
RESISTOR
12kΩ
100kΩ
1.0MΩ
CAPACITOR
1000pF
1000pF
1000pF
TYPICAL FREQUENCY
100kHz
10kHz
1kHz
TABLE 2
Driver Requirements for Overriding Scan Oscillator Input
Power Supply (V)
5
10
15
7055-012703-2
Sink Current
1.0mA
4.5mA
10.0mA
Source Current
0
0
0
LSI [ LSI COMPUTER SYSTEMS ]
