LSI/CSI
UL
®
LS7060/7062
(631) 271-0400 FAX (631) 271-0405
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
32 BIT/DUAL 16 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
FEATURES:
• DC to 15 MHz Count Frequency
• Byte Multiplexer
• DC to 1 MHz Scan Frequency
• +4.75V to +5.25V Operation (V
DD
-V
SS
)
• Three-State Data Outputs, Bus and TTL Compatible
• Inputs TTL and CMOS Compatible
• Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
Counter Systems
• Low Power Dissipation
• LS7060, LS7062 (DIP); LS7060-S, LS7062-S (SOIC)
See Figures 1 and 2
DESCRIPTION:
The LS7060/LS7062 is a monolithic, ion implanted MOS Silicon
Gate, 32 bit/dual 16 bit up counter. The IC includes latches, multi-
plexer, eight three-state binary data output drivers and output
cascading logic.
DESCRIPTION OF OPERATION:
32 (16) BIT BINARY UP COUNTER - LS7060 (LS7062)
The 32(16) bit static ripple through counter increments on the
negative edge of the input count pulse. Maximum ripple time is
4µs (2µs) - transition count of 32(16) ones to 32(16) zeros.
Guaranteed count frequency is DC to 15MHz.
See Figure 9A(9B) for Block Diagram.
COUNT, ALT COUNT
(LS7060)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry con-
tains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.
COUNT A, ALT COUNT A
(LS7062)
Input count pulses to the first 16 bit counter may be applied
through either of these two inputs. The ALT COUNT A input cir-
cuitry contains a Schmitt trigger network which allows proper
counting with “infinitely” long clock edges. A high applied to either
of these two inputs inhibits counting.
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 1µs. RESET must be high for a minimum of
300ns before next valid count can be recorded.
TEST COUNT
(LS7060)
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
7060/62-071698-1
July 1998
PIN ASSIGNMENT - TOP VIEW
18
V
DD
(+V)
17
B4 OUT
16
B5 OUT
15
B6 OUT
COUNT
ALT COUNT
B3 OUT
B2 OUT
B1 OUT
B0 OUT
RESET
CASCADE EN OUT
LSI
1
2
3
4
5
6
7
8
9
LS7060
14
B7 OUT
13
TEST COUNT
12
SCAN RESET/LOAD
11
ENABLE
10
SCAN
V
SS
(-V)
FIGURE 1
PIN ASSIGNMENT - TOP VIEW
COUNT A
ALT COUNT A
B3 OUT
B2 OUT
B1 OUT
B0 OUT
RESET
CASCADE EN OUT
V
SS
(-)
1
2
3
4
5
6
7
8
9
18
17
16
15
V
DD
(+V)
B4 OUT
B5 OUT
COUNT B
(LS7062)
Count pulses may be applied to the last 16 bits of the binary
counter through this input. The counter advances on the neg-
ative transition of these pulses.
LATCHES -
LS7060 (LS7062)
32 bits of latch are provided for storage of counter data. All latch-
es are loaded when the LOAD input is brought low for a mini-
mum of 1µs and kept low until a minimum of 4µs (2µs) has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 250ns before next negative edge of count pulse or
RESET.
LSI
B6 OUT
B7 OUT
COUNT B
SCAN RESET/LOAD
ENABLE
SCAN
LS7062
14
13
12
11
10
FIGURE 2
LSI [ LSI COMPUTER SYSTEMS ]
