UL
®
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
RBIAS
V
DD
(+V )
V
SS
(-V )
A
1
2
3
4
LS7183N
LS7184N
(631) 271-0400 FAX (631) 271-0405
April 2009
PIN ASSIGNMENT - TOP VIEW
A3800
QUADRATURE CLOCK CONVERTER
FEATURES:
• x1, x2 and x4 resolution
• Programmable output pulse width (200ns to 140µs)
• Excellent regulation of output pulse width
• TTL and low voltage CMOS compatible I/Os
• +3V to +12V operation (V
DD
- V
SS
)
•
LS7183N, LS7184N
(DIP);
LS7183N-S, LS7184N-S
(SOIC) -
See Figure 1
Applications:
• Interface incremental encoders to Up / Down Counters
(See Figure 6A and Figure 6B)
• Interface rotary encoders to Digital Potentiometers
(See Figure 7)
DESCRIPTION:
The
LS7183N
and
LS7184N
are CMOS quadrature clock converters.
Quadrature clocks derived from optical or magnetic encoders, when
applied to the A and B inputs of the
LS7183N
/
LS7184N,
are con-
verted to strings of Up Clocks and Down Clocks (LS7183N) or to a
Clock and an Up/Down direction control (LS7184N). These outputs
can be interfaced directly with standard Up/Down counters for direc-
tion and position sensing of the encoder.
INPUT/OUTPUT DESCRIPTION:
RBIAS
(Pin 1)
Input for external component connection. A resistor connected be-
tween this input and V
SS
adjusts the output clock pulse width (Tow).
V
DD
(Pin 2)
Supply Voltage positive terminal.
V
SS
(Pin 3)
Supply Voltage negative terminal.
A, B
(Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are gener-
ated from the A and B clocks according to Fig. 2. A and B inputs have
built-in immunity for noise signals less than 50ns duration (Validation
delay, T
VD
). The A and B inputs are inhibited during the occurrence of
a directional output clock (UPCK or DNCK), so that spurious clocks
resulting from encoder dither are rejected.
MODE
(Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The input
quadrature clock rate is multiplied by factors of 1, 2 and 4 in x1, x2
and x4 mode, respectively, in producing the output UP/DN clocks
(See Fig. 2). x1, x2 and x4 modes selected by the MODE input logic
levels are as follows:
Mode = 0
: x1 selected
Mode = 1
: x2 selected
Mode = Float : x4 selected
8
7
UPCK
DNCK
MODE
B
LSI
LS7183N
6
5
RBIAS
V
DD
(+V )
V
SS
(-V )
A
1
2
3
4
8
7
6
5
FIGURE 1
CLK
UP/DN
MODE
B
LS7183N - DNCK
(Pin 7)
In
LS7183N,
this is the DOWN Clock Output. This output con-
sists of low-going pulses generated when A input lags the B
input.
LS7184N - UP/DN
(Pin 7)
In
LS7184N,
this is the count direction indication output.
When A input leads the B input, the UP/DN output goes high
indicating that the count direction is UP. When A input lags
the B input, UP/DN output goes low, indicating that the count
direction is DOWN.
LS7183N - UPCK
(Pin 8)
In
LS7183N,
this is the UP Clock output. This output consists
of low-going pulses generated when A input leads the B in-
put.
LS7184N - CLK
(Pin 8)
In
LS7184N,
this is the combined UP Clock and DOWN
Clock output. The count direction at any instant is indicated
by the UP/DN output (Pin 7).
NOTE:
For the
LS7184N,
the timing of CLK and UP/DN re-
quires that the counter interfacing with
LS7184N
counts on
the rising edge of the CLK pulses.
LSI
LS7184N
7183N/84N-042709-1
LSI [ LSI COMPUTER SYSTEMS ]
