FORWARD/REVERSE (Pin 19)
This pin acts to modify the input to output sequence such
that when brought from high to low or low to high the direc-
tion of rotation will reverse. An internal pull up resistor is
provided at Pin 19 causing a logic one when left open.
SENSE INPUTS (Pins 15, 16, 17)
These inputs provide control of the output commutation
sequence as shown in Table III. S1, S2, S3 originate in
the position sensors of the motor and must sequence in
cycle code order. Hall switch "pull-up" resistors are pro-
vided at Pins 15, 16 and 17. The positive supply of the
Hall devices should be common to the chip Vss.
BRAKE (Pin 9)
A high level applied to this input unconditionally turns off
outputs 1, 2 and 3 and turns on outputs 4,5 and 6 (See
Figure 1). Transistors Q101, Q102 and Q103 cut off caus-
ing Q107, Q108 and Q109 to cut off and transistors Q104,
Q105 and Q106 turn on, shorting the windings together,
The BRAKE has priority over all other inputs. An internal
pull down resistor is provided at Pin 9 causing no braking
when left open. (Center- tapped motor configuration re-
quires a power supply disconnect transistor controlled by
the BRAKE signal - See Figure 3.)
ENABLE (Pin 10)
A high level on this input permits the output to sequence
as in Table III, while a low disables all external output driv-
ers. An internal "pull up" resistor is provided at Pin 10,
enabling when left open. Positive edges at this input will
reset the overcurrent flip-flop.
OVERCURRENT SENSE (Pin 12)
This input provides the user a way of protecting the motor
winding, drivers and power supply from an overload
condition. The user provides a fractional ohm resistor
between the negative supply and the common emitters of
the NPN drivers. This point is connected to one end of a
potentiometer (e.g. 100K ohms), the other end of which is
connected to the positive supply. The wiper pickoff is
adjusted so that all outputs are disabled for currents great-
er than the limit. The action of the input is to disable all
external output drivers. When BRAKE exists, OVER-
CURRENT SENSE will be overridden. The overcurrent
circuitry latches the overcurrent condition. The latch may
be reset by the positive edge of either the sawtooth OS-
CILLATOR or the ENABLE input. When using the EN-
ABLE input as a chopped input, the OSCILLATOR pin
should be held at V
SS
. When the ENABLE input is held
high, the OSCILLATOR must be used to reset the over-
current latch.
V TRIP (Pin 13)
This pin is used in conjunction with the sawtooth oscillator
provided on the circuit. When the voltage level applied to
V TRIP is more negative than the waveform at the OS-
CILLATOR pin, the low-side drivers will be enabled. When
V TRIP is more positive than the sawtooth OSCILLATOR
waveform the low-side drivers are disabled.
The sawtooth waveform at the OSCILLATOR pin typically var-
ies from .4 Vss to Vss-2 Volts (assuming V
DD
is at ground po-
tential). The purpose of the V TRIP input in conjunction with the
OSCILLATOR is to provide variable speed adjustment for the
motor by means of PWM of the low-side drivers.
OSCILLATOR (Pin 14)
A reisistor and capacitor connected to this pin (See Fig. 6) pro-
vide the timing components for a sawtooth OSCILLATOR. The
signal generated is used in conjunction with V TRIP to provide
PWM for variable speed applications and to reset the over-
current condition.
OUTPUTS 1, 2, 3 (Pins 2, 3, 4)
These open drain outputs are enabled as shown in Table III and
provide base current when the COMMON (Pin 5) is tied to Vss.
These outputs provide commutation only for the high-side driv-
ers. They are not pulse width modulated to control speed.
OUTPUT 4, 5, 6 (PINS 6, 7, 8)
These open drain outputs are enabled as in Table III and
provide base current to NPN transistors when the COMMON is
tied to Vss. They provide commutation and are pulse width
modulated to provide speed control.
COMMON (Pin 5)
The COMMON is connected to Vss for driving low-side drivers
and high-side level converters.
Vss (Pin 11)
Supply voltage positive terminal.
V
DD
(Pin 18)
Supply voltage negative terminal.
TYPICAL CIRCUIT OPERATION:
Figure 1 indicates an application using bipolar power tran-
sistors. The oscillator is used for motor speed control as ex-
plained under VTRIP. Only low-side drive transistors are pulse
width modulated during speed control. The outputs turn on
in pairs (See Table III). For example, two separate paths are
turned on when Q8 and Q4 are on. One path is from the pos-
itive supply through Q8, R1 and the base emitter junction of
Q101. The second is from the positive supply through Q4, R14,
the base emitter junction of Q105 and the fractional ohm re-
sistor to ground. The current in the first path is determined by
the power supply voltage, the impedance of Q8, the value of
R1 and the voltage drop across the base-emitter junction of
Q101 (0.7 Volts for a single transistor or 1.4 Volts for a Darling-
ton Transistor). The current in the second path is determined
by the power supply voltage, the impedance of Q4, the value of
R14 and the voltage drop across the base-emitter junction of
Q105. Table I provides the recommended value for R1; R2,
R3, R13, R14, and R15 are the same value.
Figure 2 indicates an application where Power FETS are used.
The nominal power supply for the LS7362 in this configuration
is 15 Volts so that the low side N channel Power FET drivers
will have 15 Volts of gate drive. Resistors R13, R14 and R15
serve to discharge the gate capacitance during FET turn-off.
The high-side P-channel FET drivers use 15 Volt Zener diodes
Z1, Z2 and Z3 to limit the gate drive. Resistors R8, R10 and
R12 are the gate capacitance discharge resistors. Table II in-
dicates the minimum value of R13 (=R14=R15) needed as a
function of output drive voltage for the low-side drivers.
7362-110292-2
LSI [ LSI COMPUTER SYSTEMS ]
