TABLE 1
UP/DOWN SIGNAL DURATION
INPUT
SHORT
34ms to 325 ms
PRE-ACTIVATION
BRIGHTNESS
Off
UP
Max.
Intermediate
POST-ACTIVATION
BRIGHTNESS
Memory **
(See Note 1)
No Change
No Change
LONG
More than 334ms
PRE-ACTIVATION
BRIGHTNESS
Off
Max.
Intermediate
POST-ACTIVATION
BRIGHTNESS
Increases from Min.
No change
Increases from pre-
touch brightness
No change
Decreases from Max.
Decreases from pre-
touch brightness
Off
DOWN
Max.
Intermediate
No Change
Off *
Off *
Off
Max.
Intermediate
* 5.6 second ramp-down from max. to off. Ramp-down time from any other brightness is proportionally shorter.
** 2.8 second ramp-up from off to max.
NOTE 1:
"Memory" refers to the brightness stored in the memory. The brightness is stored in memory when the
lamp is turned off by a short activation. First time after power-up, a short activation produces max. brightness.
INPUT/OUTPUT DESCRIPTION:
V
SS
(Pin 1)
Supply voltage positive terminal.
UP (Pin 5).
This input controls the turn-on and the conduction angle,
ø ,
of the TRIG output. A description of this is provided in the
DOZE (Pin 2)
DESCRIPTION and TABLE 1. For LS7534, a logic low level
A clock applied to this input causes the brightness to de- is the active level whereas for LS7535 a logic high level is
crease in equal increments with each negative transition the active level. LS7535 has an internal pull-down resistor
of the clock. Eventually, when the lamp becomes off, this of about 500K Ohms on this input.
input has no further effect. The lamp can be turned on
again by activating the UP input. For the transition from
DOWN (Pin 6).
maximum brightness to off, a total of 83 clock pulses are This input controls the turn-off and the conduction angle, ø,
needed at the DOZE input.
of the TRIG output. A description of this is provided in the
When either the UP or the DOWN input is active, the DESCRIPTION and TABLE 1. For LS7534, a logic low level
DOZE input is disabled.
is the active level, whereas for LS7535 a logic high level is
the active level. LS7535 has an internal pull-down resistor
CAP (Pin 3)
of about 500K Ohms on this input.
The CAP input is for external component connection for
the PLL filter capacitor. A capacitor of 0.047µF ± 20%
V
DD
(Pin 7).
should be used at this input.
Supply voltage negative terminal.
SYNC (Pin 4).
The AC line frequency (50Hz/60Hz), when applied to this
input, synchronizes all internal timings through a phase
lock loop. The signal for this input may be obtained from
the line voltage by employing the circuit arrangement
shown in the application examples.
TRIG (Pin 8).
The TRIG output provides a low level pulse occurring every
half-cycle of the SYNC signal. The conduction angle,
ø,
of
the TRIG output can be varied within the range of 41o to
159o by means of either the UP or the DOWN input.
7534/35-080796-2
LSI [ LSI COMPUTER SYSTEMS ]
