UL
®
LSI/CSI
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
RS2
RS1
RS0
NC
DB0
DB1
DB2
DB3
DB4
LS7766
(631) 271-0400 FAX (631) 271-0405
October 2007
A3800
32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER
FEATURES:
• Direct interface with Incremental Encoders
• Read/write registers for count and I/O modes. Count modes
include: non-quadrature (Up/Down), quadrature (x1, x2, x4.)
free-run, non-recycle, modulo-n and range limit
• Programmable IOs for Index and Marker Flags
• Separate mode-control registers for each axis
• 40MHz count frequency at 5V; 20MHz count frequency at 3V
• Sets of 32-bit counters, input registers, output registers,
comparators and octal Status registers for each axis
• Digital filtering of the input quadrature clocks
for noise immumity.
• Pin selectable 3-state Hex / Octal bus
• 3V to 5.5V operating voltage range
• Available in four different configurations identified
by the following suffixes:
DH
= Dual-axis with pin selectable Hex/Octal IO Bus
DO
= Dual-axis Octal IO Bus
SH
= Single-axis pin selectable Hex/Octal IO Bus
SO
= Single axis Octal IO Bus
LS7766DH-TS; LS7766DO, LS7766DO-S, LS7766DO-TS;
LS7766SO, LS7766SO-S, LS7766SO-TS; LS7766SH-TS
P/N = DIP;
P/N-S
= SOIC; P/N-TS = TSSOP
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
PCKO
PCKI
RD/
WR/
CS/
NC
x1B
x1A
x1INDX/
x1FLGa
x1FLGb
x1CKO
V
SS
IO16/
x0/_x1
x0CKO
x0FLGb
x0FLGa
NC
x0INDX/
x0A
x0B
NC
LSI
DB5
10
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
NC
NC
NC
V
SS
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LS7766DH
GENERAL DESCRIPTION:
The LS7766 consists of two identical modules of 32-bit programmable
up/down counters (CNTR) with direct interface to incremental encod-
ers. The modules can be configured to operate as quadrature-clock
counters or non-quadrature up/down counters. In both quadrature and
non-quadrature modes, the modules can be further configured into
free-running, non-recycle, modulo-n and range-limit count modes. The
mode configuration is made via two octal read/write addressable
mode control registers, MCR0 and MCR1. Data can be written into a
32-bit input data register (IDR), organized in addressable Word seg-
ments using the hex IO bus or in byte segments using the octal IO
Bus. The IDR can be used to store target encoder positions and com-
pared with the CNTR for generating marker flags when the CNTR
reaches the target value. A 32-bit digital comparator is included for
monitoring the equality of the CNTR to the IDR. Snapshots of the
CNTR value can be stored in a read-addressable 32-bit output data
register (ODR). The ODR can be read in Word segments or byte seg-
ments in accordance with the selected bus width. Data transfers
among the registers and various register reset functions are per-
formed by means of a write-addressable octal transfer control register
(TCR). A read-addressable octal status register (STR), stores the
count related status information such as CNTR overflow, underflow,
count direction, etc.
7766-102307-1
Pin Assignment - Top View
LSI [ LSI COMPUTER SYSTEMS ]
