'$7$ 6+((7
$35,/ ìääç
/;3çìí
5HYLVLRQ íïí
/RZð-LWWHU 0XOWLð5DWH &ORFN $GDSWHU õ&/$'ô
*HQHUDO 'HVFULSWLRQ
7KH /;3çìí 0XOWLð5DWH &ORFN $GDSWHU õ&/$'ô RIIHUV
SLQðVHOHFWDEOH IUHTXHQF\ FRQYHUVLRQ EHWZHHQ 7ì DQG (ì
UDWHV DV ZHOO DV å DGGLWLRQDO UDWHV IURP ìïèéé 0+] WR
åïìäë 0+]ï 7KH RXWSXW FORFN LV IUHTXHQF\ðORFNHG WR WKH
LQSXW FORFNï :KHQ DQ LQSXW IUDPH V\QF SXOVH LV SURYLGHGñ
WKH &/$' SKDVHðORFNV WKH LQSXW DQG RXWSXW FORFNV
WRJHWKHUñ DQG ORFNV WKH å N+] RXWSXW IUDPH V\QF SXOVH WR
WKH LQSXW IUDPH V\QF SXOVHï 7KH IUDPH V\QF SRODULW\ LV DOVR
SLQðVHOHFWDEOHï
)LYH GLIIHUHQW KLJK IUHTXHQF\ RXWSXW FORFNV DUH DYDLODEOH
IRU DSSOLFDWLRQV ZKLFK UHTXLUH D KLJKHUðWKDQðEDXG UDWH
EDFNSODQH RU V\VWHP FORFNï 7KH KLJK IUHTXHQF\ RXWSXW
õ+)2ô FORFN YDULHV ZLWK WKH LQSXW FORFN IUHTXHQF\ï
/HYHO 2QH©V SDWHQWHG ORFNLQJ PHWKRG HQDEOHV WKH &/$' WR
SHUIRUP IUHTXHQF\ FRQYHUVLRQ ZLWK QR H[WHUQDO FRPSRð
QHQWVñ ZKLOH JHQHUDWLQJ YHU\ OLWWOH MLWWHU RQ WKH RXWSXW FORFNï
7KH FRQYHUVLRQ LV GLJLWDOO\ FRQWUROOHG VR WKH RXWSXW FORFN LV
DV DFFXUDWH DV WKH LQSXW FORFNï
7KH &/$' LV DQ DGYDQFHG &026 GHYLFHï ,W UHTXLUHV RQO\
D VLQJOH òè 9 SRZHU VXSSO\ï
)HDWXUHV
‡ 7UDQVODWHV EHWZHHQ ìí GLIIHUHQW IUHTXHQFLHVï
*HQHUDWHV EDVLF DQG KLJK IUHTXHQF\ RXWSXW FORFNV DQG
IUDPH V\QF IURP DQ LQSXW FORFN DQG LWV IUDPH V\QFï
‡ +LJK )UHTXHQF\ 2XWSXW FORFN IRU KLJKHUðWKDQðEDXG UDWH
EDFNSODQH V\VWHPV
‡ /RZ RXWSXW MLWWHU PHHWV $7÷7 3XEOLFDWLRQ çëéìì IRU
ìïèéé 0+]ñ DQG ,78 5HFRPPHQGDWLRQ *ïåëê IRU ëïíéå
0+]
‡ 'LJLWDO FRQWURO RI IUHTXHQF\ FRQYHUVLRQ SURFHVV
‡ 1R H[WHUQDO FRPSRQHQWV
‡ 3LQðVHOHFWDEOH RSHUDWLRQ PRGH
‡ /RZðSRZHU è 9 RQO\ &026 LQ ìéðSLQ SODVWLF ',3 RU
ëåðSLQ 3/&&
ì
ë
ê
é
è
ç
æ
å
ä
ìí
ìì
ìë
ìê
ìé
ìè
$SSOLFDWLRQV
‡ ,QWHUQDO WLPLQJ V\VWHP IRU &KDQQHO %DQNVñ 'LJLWDO /RRS
&DUULHUVñ 0XOWLSOH[HUVñ ,QWHUQDO 7LPLQJ *HQHUDWRUVñ HWFï
‡ &RQYHUVLRQ EHWZHHQ 7ìî(ì FORFN UDWHV DQG KLJKHU IUHð
TXHQF\ EDFNSODQH UDWHV õ7ìî(ì FRQYHUWHUô
‡ 6SHFLDO EDFNSODQH LQWHUIDFHV õHïJï 17, ëïèç 0+]ô
/;7çìí %ORFN 'LDJUDP
CLKI
Input
Divider
Analog
Phase-Locked
Loop
Output
Divider
HFO
CLKO
Feedback
Divider
SEL
FSI
P1
P2
P3
P4
Frequency
Converter
Frame Sync
Generator
FSP
FSO
Frequency
Select
Logic
L1
çðìì
LVL1 [ LEVEL ONE ]
