®
LY6210248
Rev. 1.0
1024K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
t
RC
*
= Read Cycle Time
SYMBOL TEST CONDITION
V
DR
CE#
≧
V
CC
- 0.2V or CE2
≦0.2V
V
CC
= 1.5V
-LL
CE#
≧
V
CC
- 0.2V or CE2
≦0.2V
I
DR
Other pins at 0.2V or V
CC
- 0.2V -LLI
t
CDR
t
R
See Data Retention
Waveforms (below)
MIN.
1.5
-
-
0
t
RC
*
TYP.
-
5
5
-
-
MAX. UNIT
5.5
V
30
50
-
-
µA
µA
ns
ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE2
CE2
≦
0.2V
V
IL
V
IL
Vcc(min.)
t
R
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
LYONTEK [ Lyontek Inc. ]
