®
LY621024
Rev. 1.7
WRITE CYCLE 1
(WE# Controlled) (1,2,3,5,6)
t
WC
Address
t
AW
CE#
t
CW
CE2
t
AS
WE#
t
WHZ
Dout
(4)
High-Z
t
DW
Din
t
DH
T
OW
(4)
t
WP
t
WR
128K X 8 BIT LOW POWER CMOS SRAM
Data Valid
WRITE CYCLE 2
(CE# and CE2 Controlled) (1,2,5,6)
t
WC
Address
t
AW
CE#
t
AS
t
CW
CE2
t
WP
WE#
t
WHZ
Dout
(4)
High-Z
t
DW
Din
t
DH
t
WR
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, t
WP
must be greater than t
WHZ
+ t
DW
to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.t
OW
and t
WHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
7
LYONTEK [ Lyontek Inc. ]
