®
LY621024
Rev. 1.7
128K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
SYMBOL
TEST CONDITION
MIN.
V
DR
CE#
≧
V
CC
- 0.2V or CE2
≦
0.2V
1.5
LL
-
LLE/LLI
-
V
CC
= 1.5V
SL
25℃
-
CE#
≧
V
CC
- 0.2V
I
DR
SLE
or CE2
≦
0.2V
-
40℃
Other pins at 0.2V or V
CC
-0.2V SLI
SL
-
SLE/SLI
-
See Data Retention
0
t
CDR
Waveforms (below)
t
R
t
RC
*
TYP.
-
0.5
0.5
0.4
0.5
0.4
0.4
-
-
MAX.
5.5
12
30
2
2
5
8
-
-
UNIT
V
µA
µA
µA
µA
µA
µA
ns
ns
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
t
RC
*
= Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE2
CE2
≦
0.2V
V
IL
V
IL
Vcc(min.)
t
R
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
8
LYONTEK [ Lyontek Inc. ]
