®
LY621024
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.7
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
LL
MIN.
1.5
-
-
TYP. MAX. UNIT
VDR
-
5.5
12
30
V
0.5
0.5
A
µ
µ
LLE/LLI
SL
SLE
SLI
SL
A
VCC = 1.5V
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
℃
-
-
0.4
0.5
2
2
25
A
µ
µ
Data Retention Current
IDR
℃
A
40
Other pins at 0.2V or VCC-0.2V
-
-
0.4
0.4
5
8
A
µ
A
µ
SLE/SLI
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
CE2 ≦ 0.2V
CE2
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
LYONTEK [ Lyontek Inc. ]
