®
LY621024
Rev. 1.7
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled) (1,2)
t
RC
Address
t
AA
Dout
Previous Data Valid
t
OH
Data Valid
READ CYCLE 2
(CE# and CE2 and OE# Controlled) (1,3,4,5)
t
RC
Address
t
AA
CE#
t
ACE
CE2
OE#
t
OE
t
OLZ
t
CLZ
Dout
High-Z
t
OH
t
OHZ
t
CHZ
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low
.,
CE2 = high
.
3.Address must be valid prior to or coincident with CE# = low
,
CE2 = high; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
6
LYONTEK [ Lyontek Inc. ]
