®
LY622568
Rev. 2.4
256K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
V
CC
for Data Retention
V
DR
CE#
≧
V
CC
- 0.2V or CE2
≦
0.2V
LL
V
CC
= 1.5V
CE#
≧
V
CC
- 0.2V
Data Retention Current
I
DR
SL
or CE2
≦
0.2V
Other pins at 0.2V or V
CC
-0.2V
SL
See Data Retention
Chip Disable to Data
t
CDR
Waveforms (below)
Retention Time
Recovery Time
t
R
t
RC
*
= Read Cycle Time
MIN.
1.5
-
25℃
40℃
TYP.
-
1
1
1
1
-
-
MAX.
5.5
20
4
4
15
-
-
-
-
-
0
t
RC
*
UNIT
V
µA
µA
µA
µA
ns
ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE2
CE2
≦
0.2V
V
IL
V
IL
Vcc(min.)
t
R
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
7
LYONTEK [ Lyontek Inc. ]
