®
LY62256
Rev. 2.9
32K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
SYMBOL
TEST CONDITION
V
DR
CE#
≧
V
CC
- 0.2V
LL/LLE/LLI
SL
25℃
V
CC
= 1.5V
SLE
CE#
≧
V
CC
- 0.2V
I
DR
SLI
40℃
Others at 0.2V or V
CC
-0.2V
SL
SLE/SLI
See Data Retention
t
CDR
Waveforms (below)
t
R
MIN.
1.5
-
-
-
-
-
0
t
RC
*
TYP.
-
0.5
0.5
1
0.5
0.5
-
-
MAX.
5.5
20
2
3
8
15
-
-
UNIT
V
µA
µA
µA
µA
µA
ns
ns
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
t
RC
*
= Read Cycle Time
DATA RETENTION WAVEFORM
V
DR
≧
1.5V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
7
LYONTEK [ Lyontek Inc. ]
