Signal Description
Pin Description
The TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII
interface. The MAC interface pins are 3.3V tolerant.
Table 3:
TBI Interface
117-TFBGA 96-BCC 128-PQFP Pin Name
Pin
Description
Pin #
Pin #
Pin #
Type
E2
8
14
GTX_CLK/
TBI_TXCLK
I
TBI Transmit Clock. In TBI mode, GTX_CLK
is used as TBI_TXCLK. TBI_TXCLK is a 125
MHz transmit clock.
TBI_TXCLK provides a 125 MHz clock refer-
ence for TX_EN, TX_ER, and TXD[7:0].
D1
4
10
TX_CLK/RCLK1 O, Z
TBI 62.5 MHz Receive Clock- even code
group. In TBI mode, TX_CLK is used as
RCLK1.
J2
J1
20
19
18
17
16
14
12
11
29
28
26
25
24
20
19
18
TXD[7]
TXD[6]
TXD[5]
TXD[4]
TXD[3]
TXD[2]
TXD[1]
TXD[0]
I
TBI Transmit Data. TXD[7:0] presents the
data byte to be transmitted onto the cable.
H3
H1
H2
G3
G2
F1
TXD[9:0] are synchronous to GTX_CLK.
Inputs TXD[7:4] should be tied low if not
used (e.g., RTBI mode).
E1
9
16
TX_EN/
TXD8
I
I
TBI Transmit Data. In TBI mode, TX_EN is
used as TXD8.
TXD[9:0] are synchronous to GTX_CLK.
F2
7
13
TX_ER/
TXD9
TBI Transmit Data. In TBI mode, TX_ER is
used as TXD9.
TXD[9:0] are synchronous to GTX_CLK.
TX_ER should be tied low if not used (e.g.,
RTBI mode).
C1
2
7
RX_CLK/
RCLK0
O, Z
O, Z
TBI 62.5 MHz Receive Clock- odd code
group. In the TBI mode, RX_CLK is used
as RCLK0.
C5
A2
A1
C4
B3
C3
D3
B2
86
87
89
90
91
93
92
95
120
121
123
124
125
126
128
3
RXD[7]
RXD[6]
RXD[5]
RXD[4]
RXD[3]
RXD[2]
RXD[1]
RXD[0]
TBI Receive Data code group [7:0]. In the
TBI mode, RXD[7:0] present the data byte to
be transmitted to the MAC. Symbols
received on the cable are decoded and pre-
sented on RXD[7:0].
RXD[7:0] are synchronous to RCLK0 and
RCLK1.
B1
94
4
RX_DV/
RXD8
O, Z
TBI Receive Data code group bit 8. In the
TBI mode, RX_DV is used as RXD8.
RXD[9:0] are synchronous to RCLK0 and
RCLK1.
Copyright © 2009 Marvell
March 4, 2009, Advance
Doc. No. MV-S105540-00, Rev. --
Document Classification: Proprietary Information
Page 15
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
