88EM8010/88EM8011
Datasheet
Table 2:
Pi n #
1
Pin Descriptions
P in N a m e
PGND
D e sc r ip ti o n
Power Ground
Connected to the source of the primary MOSFET. The PCB trace from the power ground to the
source of the MOSFET must be kept as short as possible. To avoid any switching noise
interruption on signal processing, PGND and SGND remain separate inside the IC.
Signal Ground
Must be connected to the power ground with Kelvin sensing connection, so that SGND has
dedicated trace and connections and provides noiseless environment for the signal processing.
Current Sense
Sense resistor varies for different loads. Pin used for current shaping and for over current
protection. Please refer to
Voltage Input
• Connects to resistive divider at input AC line “phase” to GND. Voltage applied is a half
rectified sine wave scaled down by the input resistive divider.
• Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is
recommended to be designed from the input AC “phase” to GND in order to reduce the
standby power. Higher impedance is preferred with the right PCB design on this pin signal.
• Voltage is compared with a threshold reference (V
VIN_BR
) to detect the zero-cross location
of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is
used to generate the current reference.
• Brown-out protection
1
function is also provided by this pin. A resistor devider with a 100:1
ratio from the highside resistor to the lowside resistor is corresponding to the “brown-out
protection” input voltage as 50V (RMS). Increasing that raio will increase the “brown-out
voltage”. Please refer to footnote
1
for further explaination.
Feedback
The output voltage is scaled to 2.5V with 100% rated value. Transition from soft start to normal
regulation at 87.5% rated V
FB
. Over voltage shutdown SW gate signal at 107% rated V
FB
and
recover once below V
FB_OVP
. There is another threshold (V
FB_OVP_LATCH
) as 3.77V on the FB
pin. When FB Voltage reaches V
FB_OVP_LATCH
, SW signal is shutdown and latched until
another VDD power on reset.
EN: Enable/Shutdown
• At V
FB
>V
FB_EN
5)
IC is enabled.
• Pulling this pin to V
FB
< V
FB_SHDN
disables the chip back to sleep mode
Note: A 200k resistor inside IL between FB pin to SGND. This should be included in the
calculation for the design of the output voltage feedback resistor devider.
No Connect
Float this pin.
IC Supply Voltage
Nominal voltage is 12V (typical) and the Under Voltage Lockout (UVLO) for V
DD
<V
DD_UVLO
When V
DD
< V
DD_UVLO
, IC is shut down. Start voltage of IC is V
DD_ON
5)
and
maximum voltage is 16V (Table
It should be clamped by a Zener for protection in the system
design.
Switch
PWM gate signal for the boost switch. Connects to the gate of external boost MOSFET. It is the
DSP core output for ON/OFF time buffered through the internal adaptive driver.
2
SGND
3
ISNS
4
VIN
5
FB/EN
6
7
NC
VDD
8
SW
1. Brown-out voltage is determined by R
a
, R
b
, and R
c
as shown in
Please refer to
for a further
understanding.
Doc. No. MV-S104861-01 Rev. –
Page 12
Document Classification: Proprietary
Copyright © 2009 Marvell
September 30, 2009, 2.00
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
